Ashis Kumar Mal

According to our database1, Ashis Kumar Mal authored at least 33 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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On csauthors.net:

Bibliography

2024
A Survey on Hardware Accelerator Design of Deep Learning for Edge Devices.
Wirel. Pers. Commun., August, 2024

2023
Performance of Novel Adaptive Schemes for Cognitive Full-Duplex Relaying-Based Downlink Cooperative NOMA.
IEEE Trans. Wirel. Commun., May, 2023

2022
Cooperative Mode Switching-Based Cognitive NOMA With Transmit Antenna and User Selection.
IEEE Trans. Signal Inf. Process. over Networks, 2022

Fuzzy Logic-Based Energy-Optimal Collinear DF Relay Placement in Two-Hop η -μ Fading Channel.
Int. J. Wirel. Inf. Networks, 2022

2021
A cost-effective alertness-rating tool to enable situational awareness among on-duty static security guards in Covid-19 pandemic.
J. Reliab. Intell. Environ., 2021

Performance of an Adaptive Cooperative NOMA Scheme with Transmit Antenna Selection.
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2021

2020
Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications.
J. Circuits Syst. Comput., 2020

Time-Domain Smart Temperature Sensor Using Current Starved Inverters and Switched Ring Oscillator-Based Time-to-Digital Converter.
Circuits Syst. Signal Process., 2020

An Efficient NoC-based ANN Framework for Epileptic Seizure Recognition.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

2019
All MOS noise-shaped time-mode temperature sensor.
Integr., 2019

Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms.
IET Circuits Devices Syst., 2019

Symbiotic organisms search algorithm for optimal design of CMOS two-stage op-amp with nulling resistor and robust bias circuit.
IET Circuits Devices Syst., 2019

Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach.
Comput. Electr. Eng., 2019

A cost-effective system for triggering alarm to distracted drivers/ nurses.
Comput. Electr. Eng., 2019

2018
Performance enhancement of a VCO using symbolic modelling and optimisation.
IET Circuits Devices Syst., 2018

2017
Optimal Location of Energy Efficient DF Relay Node in κ - μ Fading Channel.
Wirel. Pers. Commun., 2017

2015
Sealed-bid auction: a cryptographic solution to bid-rigging attack in the collusive environment.
Secur. Commun. Networks, 2015

Analysis of resistive load ring oscillator.
Proceedings of the 2nd IEEE International Conference on Recent Trends in Information Systems, 2015

An integrated routing and offset-time adaptation scheme for OBS network.
Proceedings of the 2015 International Conference on Distributed Computing and Networking, 2015

2014
Practical Receipt-Free Sealed-Bid Auction in the Coercive Environment.
IACR Cryptol. ePrint Arch., 2014

2013
A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
Routing Scheme for OBS Networks.
JOCN, 2012

Coercion Resistant MIX for Electronic Auction.
Proceedings of the Information Systems Security, 8th International Conference, 2012

2010
Impact of Burst Assembly Algorithms on Data Loss in OBS Networks Under Time-Correlated Traffic Input.
JOCN, 2010

A Closed Form Slew Evaluation Approach Using Burr's Distribution Function for High Speed On-Chip RC Interconnects.
Proceedings of the Information Processing and Management, 2010

Design of DXT architecture using current switched integrator.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008
Delay Estimation for On-Chip VLSI Interconnect using Weibull Distribution Function.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

Interconnect Slew Metric Using Nakagami-M Distribution.
Proceedings of the First International Conference on Emerging Trends in Engineering and Technology, 2008

2004
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Sampled analog architecture for DCT and DST.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Digital controlled analog architecture for DCT and DST using capacitor switching.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A generalized analog architecture for DCT, DST and its inverse.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
Analog sampled data architecture for discrete Hartley transform for prime N.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003


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