Asha Balijepalli

According to our database, Asha Balijepalli authored at least 7 papers between 2007 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation.

Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao

IEEE Trans. Very Large Scale Integr. Syst., 2010

2009

Compact modeling of a PD SOI MESFET for wide temperature designs.

Asha Balijepalli, Joseph Ervin, William Lepkowski, Yu Cao, Trevor J. Thornton

Microelectron. J., 2009

The Predictive Technology Model in the Late Silicon Era and Beyond.

Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao

Found. Trends Electron. Des. Autom., 2009

2008

A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design.

Saurabh Sinha, Asha Balijepalli, Yu Cao

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Compact Modeling of a PD SOI MESFET for Wide Temperature Designs.

Asha Balijepalli, Joseph Ervin, Yu Cao, Trevor Thornton

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Compact modeling of carbon nanotube transistor for early stage process-design exploration.

Asha Balijepalli, Saurabh Sinha, Yu Cao

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.

Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao

Proceedings of the 44th Design Automation Conference, 2007