Aseem Agarwal

According to our database1, Aseem Agarwal authored at least 11 papers between 2002 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2005
Statistical Timing Based Optimization using Gate Sizing.
Proceedings of the 2005 Design, 2005

Circuit optimization using statistical static timing analysis.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Statistical clock skew analysis considering intradie-process variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Statistical gate delay model considering multiple input switching.
Proceedings of the 41th Design Automation Conference, 2004

2003
Statistical timing analysis using bounds and selective enumeration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Statistical Clock Skew Analysis Considering Intra-Die Process Variations.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical Timing Analysis Using Bounds.
Proceedings of the 2003 Design, 2003

Computation and Refinement of Statistical Bounds on Circuit Delay.
Proceedings of the 40th Design Automation Conference, 2003

Statistical delay computation considering spatial correlations.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Statistical timing analysis using bounds and selective enumeration.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002


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