Asako Toda

According to our database, Asako Toda authored at least 5 papers between 2013 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O.

Kaveh Hosseini, Edwin Kok, Sergey Y. Shumarayev, Daniel Jeong, Allen Chan, Austin Katzin, Songtao Liu, Radek Roucka, Manan Raval, Minh Mac, Chia-Pin Chiu, Thungoc Tran, Kumar Abhishek Singh, Sangeeta Raman, Yanjing Ke, Chen Li, Li-Fan Yang, Paulo Chao, Haiwei Lu, Fernando Luna, Xiaoqian Li, Tim Tri Hoang, Arnab Sarkar, Asako Toda, Ravi Mahajan, Nitin Deshpande, Conor O'Keeffe, Uma Krishnamoorthy, Vladimir Stojanovic, Christopher Madden, Chong Zhang, Matt Sysak, Pavan Bhargava, Chen Sun, Mark Wade

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO.

Kaveh Hosseini, Edwin Kok, Sergey Y. Shumarayev, Chia-Pin Chiu, Arnab Sarkar, Asako Toda, Yanjing Ke, Allen Chan, Daniel Jeong, Mason Zhang, Sangeeta Raman, Thungoc Tran, Kumar Abhishek Singh, Pavan Bhargava, Chong Zhang, Haiwei Lu, Ravi Mahajan, Xiaoqian Li, Nitin Deshpande, Conor O'Keeffe, Tim Tri Hoang, Uma Krishnamoorthy, Chen Sun, Roy Meade, Vladimir Stojanovic, Mark Wade

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

2015

A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects.

Akinori Hayakawa, Masaya Kibune, Asako Toda, Shinsuke Tanaka, Takasi Simoyama, Yanfei Chen, Tomoyuki Akiyama, Shigekazu Okumura, Takeshi Baba, Tomoyuki Akahoshi, Seiji Ueno, Kazunori Maruyama, Masahiko Imai, Jian Hong Jiang, Pradip Thachile, Tamer Riad, Shigeaki Sekiguchi, Suguru Akiyama, Yu Tanaka, Ken Morito, Daisuke Mizutani, Toshihiko Mori, Takuji Yamamoto, Hiroji Ebe

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI.

Yanfei Chen, Masaya Kibune, Asako Toda, Akinori Hayakawa, Tomoyuki Akiyama, Shigeaki Sekiguchi, Hiroji Ebe, Nobuhiro Imaizumi, Tomoyuki Akahoshi, Suguru Akiyama, Shinsuke Tanaka, Takasi Simoyama, Ken Morito, Takuji Yamamoto, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS.

Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013