Arya Balachandran

According to our database, Arya Balachandran authored at least 3 papers between 2017 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS.

Arya Balachandran, Yong Chen, Chirn Chye Boon

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

A 0.013-mm² 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS.

Arya Balachandran, Yong Chen, Chirn Chye Boon

IEEE Trans. Very Large Scale Integr. Syst., 2018

2017

Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V process.

Tushar Krishna, Arya Balachandran, Siau Ben Chiah, Li Zhang, Bing Wang, Cong Wang, Kenneth Eng-Kian Lee, Jürgen Michel, Li-Shiuan Peh

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017