Arvind Rajawat

Orcid: 0000-0002-7803-6543

According to our database1, Arvind Rajawat authored at least 14 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
FPGA implementation of PUF based key generator for secure communication in IoT.
Integr., March, 2023

2022
Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC.
Integr., 2022

2020
An Accurate and Quick ANN-Based System-Level Dynamic Power Estimation Model Using LLVM IR Profiling for FPGA Designs.
IEEE Embed. Syst. Lett., 2020

2019
Fast and Accurate System-Level Power Estimation Model for FPGA-Based Designs.
J. Circuits Syst. Comput., 2019

2018
Fast and efficient power estimation model for FPGA based designs.
Microprocess. Microsystems, 2018

2016
Area and Throughput Analysis of Different AES Architectures for FPGA Implementations.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Performance evaluation of circuit level approaches for radiation hardened primitive gates.
Proceedings of the 2016 International Conference on Advances in Computing, 2016

2015
Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System.
Int. J. Reconfigurable Comput., 2015

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems.
CoRR, 2015

Instruction cache design space exploration for embedded software applications.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2013
Recent trends in embedded system software performance estimation.
Des. Autom. Embed. Syst., 2013

A Survey of Embedded Software Profiling Methodologies.
CoRR, 2013

Dominant block guided optimal cache size estimation to maximize IPC of embedded software.
CoRR, 2013

2000
nterface Synthesis: Issues and Approaches.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000


  Loading...