Arvind P. Singh

According to our database, Arvind P. Singh authored at least 4 papers between 2007 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS.

Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Vasant Hoskote, Nitin Borkar, Shekhar Borkar

IEEE J. Solid State Circuits, 2008

2007

A 5-GHz Mesh Interconnect for a Teraflops Processor.

Yatin Hoskote, Sriram R. Vangal, Arvind P. Singh, Nitin Borkar, Shekhar Borkar

IEEE Micro, 2007

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS.

Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Priya Iyer, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS.

Amit Kumar, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha

Proceedings of the 25th International Conference on Computer Design, 2007