Arvin Shahani

According to our database, Arvin Shahani authored at least 5 papers between 1997 and 2003.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2003

40-43-Gb/s OC-768 16: 1 MUX/CMU chipset with SFI-5 compliance.

Hai Tao, Derek K. Shaeffer, Min Xu, Saied Benyamin, Vincent Condito, Steffen Kudszus, Qinghung Lee, Adrian Ong, Arvin Shahani, Xiaomin Si, Wayne Wong, Maurice Tarsia

IEEE J. Solid State Circuits, 2003

A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1: 16 demultiplexer in SiGe technology.

Adrian Ong, Saied Benyamin, Jason Cancio, Vincent Condito, Tad Labrie, Qinghung Lee, John Paul Mattia, Derek K. Shaeffer, Arvin Shahani, Xiaomin Si, Hai Tao, Maurice Tarsia, Wayne Wong, Min Xu

IEEE J. Solid State Circuits, 2003

1998

Low-power dividerless frequency synthesis using aperture phase detection.

Arvin Shahani, Derek K. Shaeffer, Sunderarajan S. Mohan, Hirad Samavati, Hamid R. Rategh, Maria del Mar Hershenson, Min Xu, C. Patrick Yue, Daniel J. Eddleman, Mark A. Horowitz, Thomas H. Lee

IEEE J. Solid State Circuits, 1998

A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters.

Derek K. Shaeffer, Arvin Shahani, Sunderarajan S. Mohan, Hirad Samavati, Hamid R. Rategh, Maria del Mar Hershenson, Min Xu, C. Patrick Yue, Daniel J. Eddleman, Thomas H. Lee

IEEE J. Solid State Circuits, 1998

1997

A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver.

Arvin Shahani, Derek K. Shaeffer, Thomas H. Lee

IEEE J. Solid State Circuits, 1997