Aruna Payala

According to our database, Aruna Payala authored at least 2 papers in 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Fully Integrated 1 GHz 8A I_max Step-Down and Step-Up Switched Capacitor Voltage Regulator in 3 nm FinFET Technology Featuring Auto Mode Transition.

Arvind Raghavan, Keng Chen, Huanhuan Zhang, Sivaraman Masilamani, Tamir Salus, Rachid Rayess, Gayathri Devi Sridharan, Aruna Payala, Jianrong Chen

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024

28.6 An 87% Efficient 2V-Input, 200A Voltage Regulator Chiplet Enabling Vertical Power Delivery in Multi-kW Systems-on-Package.

Rinkle Jain, Shunjiang Xu, Rajiv Kaushal, Carlos Mariscal, Humberto Caballero, Tamir Salus, Christopher Schaef, Anup Deka, Aruna Payala, Keng Chen, Huong Do, Jonathan Douglas

Proceedings of the IEEE International Solid-State Circuits Conference, 2024