Aruna Jayasena
Orcid: 0000-0002-8347-5065
According to our database1,
Aruna Jayasena
authored at least 15 papers
between 2022 and 2024.
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Bibliography
2024
HIVE: Scalable Hardware-Firmware Co-Verification Using Scenario-Based Decomposition and Automated Hint Extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
ACM Trans. Design Autom. Electr. Syst., May, 2024
ACM Comput. Surv., May, 2024
CISELeaks: Information Leakage Assessment of Cryptographic Instruction Set Extension Prototypes.
IACR Cryptol. ePrint Arch., 2024
CoRR, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023
ACM J. Emerg. Technol. Comput. Syst., January, 2023
2022
J. Hardw. Syst. Secur., 2022
Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022