Arun Subramaniyan

According to our database, Arun Subramaniyan authored at least 23 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks.

Charles Eckert, Arun Subramaniyan, Xiaowei Wang, Charles Augustine, Ravishankar Iyer, Reetuparna Das

IEEE Trans. Computers, June, 2023

GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.

Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2021

In-/Near-Memory Computing

Daichi Fujiki, Xiaowei Wang, Arun Subramaniyan, Reetuparna Das

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01772-8, 2021

Accelerated Systems for Pattern Matching.

Arun Subramaniyan

PhD thesis, 2021

A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array.

Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw

IEEE J. Solid State Circuits, 2021

GenomicsBench: A Benchmark Suite for Genomics.

Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees.

Arun Subramaniyan, Jack Wadden, Kush Goliya, Nathan Ozog, Xiao Wu, Satish Narayanasamy, David T. Blaauw, Reetuparna Das

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing.

Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester

IEEE J. Solid State Circuits, 2020

17.3 GCUPS Pruning-Based Pair-Hidden-Markov-Model Accelerator for Next-Generation DNA Sequencing.

Xiao Wu, Arun Subramaniyan, Zhehong Wang, Satish Narayanasamy, Reetu Das, David T. Blaauw

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array.

Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks.

Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Dennis Sylvester, David T. Blaauw, Reetuparna Das, Ravi R. Iyer

IEEE Micro, 2019

A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration.

Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata.

Kevin Angstadt, Arun Subramaniyan, Elaheh Sadredini, Reza Rahimi, Kevin Skadron, Westley Weimer, Reetuparna Das

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

GenAx: A Genome Sequencing Accelerator.

Daichi Fujiki, Arun Subramaniyan, Tianjun Zhang, Yu Zeng, Reetuparna Das, David T. Blaauw, Satish Narayanasamy

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017

Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding.

Muhammad Shafique, Semeen Rehman, Florian Kriebel, Muhammad Usman Karim Khan, Bruno Zatt, Arun Subramaniyan, Bruno Boessio Vizzotto, Jörg Henkel

IEEE Trans. Computers, 2017

Cache automaton.

Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Parallel Automata Processor.

Arun Subramaniyan, Reetuparna Das

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Compute Caches.

Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David T. Blaauw, Reetuparna Das

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores.

Arun Subramaniyan, Semeen Rehman, Muhammad Shafique, Akash Kumar, Jörg Henkel

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Cache Automaton: Repurposing Caches for Automata Processing.

Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Reliability-Aware Adaptations for Shared Last-Level Caches in Multi-Cores.

Florian Kriebel, Semeen Rehman, Arun Subramaniyan, Segnon Jean Bruno Ahandagbe, Muhammad Shafique, Jörg Henkel

ACM Trans. Embed. Comput. Syst., 2016

2015

An adaptive migration-replication scheme (AMR) for shared cache in chip multiprocessors.

Nitin Chaturvedi, Arun Subramaniyan, S. Gurunarayanan

J. Supercomput., 2015

R²Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores.

Florian Kriebel, Arun Subramaniyan, Semeen Rehman, Segnon Jean Bruno Ahandagbe, Muhammad Shafique, Jörg Henkel

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015