Arun Ravindran

Orcid: 0000-0001-9391-2428

According to our database1, Arun Ravindran authored at least 34 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Understanding Policy and Technical Aspects of AI-Enabled Smart Video Surveillance to Address Public Safety.
CoRR, 2023

Evaluating Kubernetes at the Edge for Fault Tolerant Multi-Camera Computer Vision Applications.
Proceedings of the 23rd IEEE/ACM International Symposium on Cluster, 2023

2022
Understanding Ethics, Privacy, and Regulations in Smart Video Surveillance for Public Safety.
CoRR, 2022

VEI: a multicloud edge gateway for computer vision in IoT.
Proceedings of the 1st Workshop on Middleware for the Edge, 2022

2021
Mez: An Adaptive Messaging System for Latency-Sensitive Multi-Camera Machine Vision at the IoT Edge.
IEEE Access, 2021

2020
Mez: A Messaging System for Latency-Sensitive Multi-Camera Machine Vision at the IoT Edge.
CoRR, 2020

A Recurrent Neural Network Based Patch Recommender for Linux Kernel Bugs.
CoRR, 2020

Scalable Approximate Computing Techniques for Latency and Bandwidth Constrained IoT Edge.
Proceedings of the Science and Technologies for Smart Cities, 2020

2019
Latency Control for Distributed Machine Vision at the Edge Through Approximate Computing.
Proceedings of the Edge Computing - EDGE 2019, 2019

2018
An Edge Datastore Architecture For Latency-Critical Distributed Machine Vision Applications.
Proceedings of the USENIX Workshop on Hot Topics in Edge Computing, 2018

2017
Online distribution channel increases article usage on Mendeley: a randomized controlled trial.
Scientometrics, 2017

Edge datastore for distributed vision analytics: poster.
Proceedings of the Second ACM/IEEE Symposium on Edge Computing, San Jose / Silicon Valley, 2017

2014
Energy Efficient Soft Real-Time Computing through Cross-Layer Predictive Control.
Proceedings of the 9th International Workshop on Feedback Computing, 2014

2013
A statistical machine learning based modeling and exploration framework for run-time cross-stack energy optimization.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

A Cross-Stack Predictive Control Framework for Multimedia Applications.
Proceedings of the 2013 IEEE International Symposium on Multimedia, 2013

2012
Performance Modeling of Shared Memory Multiple Issue Multicore Machines.
Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

Estimating correlation for a real-time measure of connectivity.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

2011
A machine learning approach to modeling power and performance of chip multiprocessors.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2009
Efficient parallel testing and diagnosis of digital microfluidic biochips.
ACM J. Emerg. Technol. Comput. Syst., 2009

Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer.
Proceedings of the FCCM 2009, 2009

A multi-threaded DNA tag/anti-tag library generator for multi-core platforms.
Proceedings of the 2009 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2009

2008
A stream chip-multiprocessor for bioinformatics.
SIGARCH Comput. Archit. News, 2008

Reduced dimensional HRTF processing for gaming environments.
Proceedings of the International Conference on Advances in Computer Entertainment Technology, 2008

2007
Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters.
J. Low Power Electron., 2007

2006
Power Optimized Design of CMOS Programmable Gain Amplifiers.
J. Low Power Electron., 2006

Multiple fault diagnosis in digital microfluidic biochips.
ACM J. Emerg. Technol. Comput. Syst., 2006

Automated design flow for diode-based nanofabrics.
ACM J. Emerg. Technol. Comput. Syst., 2006

2005
A low input impedance fully differential CMOS transresistance amplifier using cascode regulation.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A low voltage CMOS transresistance-based variable gain amplifier.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A novel queuing architecture for background calibration of pipeline ADCs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Digital error correction and calibration of gain non-linearities in a pipelined ADC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A reconfigurable low IF-zero IF receiver architecture for multi-standard wide area wireless networks.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
A digitally generated exponential function for dB-linear CMOS variable gain amplifiers.
Proceedings of the 14th International Conference on Digital Signal Processing, 2002


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