Arun Palaniappan
According to our database1,
Arun Palaniappan
authored at least 2 papers
between 2010 and 2013.
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Bibliography
2013
A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2013
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010