Arun Palaniappan

According to our database1, Arun Palaniappan authored at least 2 papers between 2010 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2010
Power Efficiency Comparisons of Interchip Optical Interconnect Architectures.
IEEE Trans. Circuits Syst. II Express Briefs, 2010


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