Arun N. Chandorkar

According to our database, Arun N. Chandorkar authored at least 15 papers between 2004 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform.

Anand D. Darji, R. Arun, S. N. Merchant, Arun N. Chandorkar

IET Comput. Digit. Tech., 2015

2014

Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform.

Anand D. Darji, Shubham Agrawal, Ankit Oza, Vipul Sinha, Aditya Verma, S. N. Merchant, Arun N. Chandorkar

IEEE Trans. Circuits Syst. II Express Briefs, 2014

High-performance hardware architectures for multi-level lifting-based discrete wavelet transform.

Anand D. Darji, Shailendra Kushwah, Shabbir N. Merchant, Arun N. Chandorkar

EURASIP J. Image Video Process., 2014

Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform.

Anand D. Darji, Saurabh Shukla, S. N. Merchant, Arun N. Chandorkar

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Flipping-based high speed VLSI architecture for 2-D lifting DWT.

Anand D. Darji, Konale Shashikanth, Ankur Limaye, S. N. Merchant, Arun N. Chandorkar

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013

Voltage and current stress induced variations in TiN/HfSi_xO_y/TiN MIM capacitors.

Durga Misra, Jyothi Kasinath, Arun N. Chandorkar

Microelectron. Reliab., 2013

Watermarking Hardware Based on Wavelet Coefficients Quantization Method.

Anand D. Darji, T. C. Lad, Shabbir N. Merchant, Arun N. Chandorkar

Circuits Syst. Signal Process., 2013

2012

Hardware efficient recursive VLSI architecture for multilevel lifting 2-D DWT.

Anand D. Darji, Nisarg Trivedi, S. N. Merchant, Arun N. Chandorkar

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

VLSI Implementation of Wavelet Based Robust Image Watermarking Chip.

T. C. Lad, Anand D. Darji, S. N. Merchant, Arun N. Chandorkar

Proceedings of the International Symposium on Electronic System Design, 2011

High speed VLSI architecture for 2-D lifting Discrete Wavelet Transform.

Anand D. Darji, Rajul Bansal, S. N. Merchant, Arun N. Chandorkar

Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010

VLSI Architecture of DWT Based Watermark Encoder for Secure Still Digital Camera Design.

Anand D. Darji, Arun N. Chandorkar, Shabbir N. Merchant, Vipul Mistry

Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

2007

Precision Low Voltage and Current References.

Brajesh Pandey, Arun N. Chandorkar

J. Low Power Electron., 2007

2006

On-chip Test and Repair of Memories for Static and Dynamic Faults.

Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar

Proceedings of the 2006 IEEE International Test Conference, 2006

Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter.

Arun N. Chandorkar, Gurvinder Singh

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2004

Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories.

Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004