Arun Gunda

According to our database, Arun Gunda authored at least 15 papers between 1995 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests.

Fan Yang, Sreejit Chakravarty, Arun Gunda, Nicole Wu, Jianyu Ning

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2012

Silicon evaluation of faster than at-speed transition delay tests.

Sreejit Chakravarty, Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2010

Multiple fault activation cycle tests for transistor stuck-open faults.

Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 2011 IEEE International Test Conference, 2010

Clock Gate Test Points.

Narendra Devta-Prasanna, Arun Gunda

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Accurate measurement of small delay defect coverage of test patterns.

Narendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

Comparative study of centralised and distributed compatibility-based test data compression.

Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda

IET Comput. Digit. Tech., 2008

2007

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.

Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Systematic Scan Reconfiguration.

Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.

Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 11th European Test Symposium, 2006

Test Generation for Open Defects in CMOS Circuits.

Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

Methods for improving transition delay fault coverage using broadside tests.

Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.

Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Should Illinois-Scan Based Architectures be Centralized or Distributed?

Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.

Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

1995

Failure Analysis for Full-Scan Circuits.

Kaushik De, Arun Gunda

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995