Arun Achyuthan

According to our database, Arun Achyuthan authored at least 4 papers between 1994 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.

Michael Clinton, Hank Cheng, Hung-Jen Liao, Robin Lee, Ching-Wei Wu, Johnny Yang, Hau-Tai Hsieh, Frank Wu, Jung-Ping Yang, Atul Katoch, Arun Achyuthan, Donald Mikan, Bryan Sheffield, Jonathan Chang

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2008

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS.

Sergey Romanovsky, Atul Katoch, Arun Achyuthan, C. O'Connell, Sreedhar Natarajan, C. Huang, Chuan-Yu Wu, Min-Jer Wang, C. J. Wang, P. Chen, R. Hsieh

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2004

Leakage Reduction techniques in a 0.13um SRAM Cell.

Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

1994

Mixed analog/digital hardware synthesis of artificial neural networks.

Arun Achyuthan, Mohamed I. Elmasry

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994