Arul Sendhil

According to our database, Arul Sendhil authored at least 6 papers between 2011 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface.

Vinod Inipodu Murugan, Narayanan Mayandi, Arul Sendhil

Proceedings of the 28th International Conference on VLSI Design, 2015

2013

A Novel Scheme to Reset through Clock.

Sanku Mukherjee, M. Thrivikraman M., Anil K. Goyal, Arul Sendhil

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems.

Sanku Mukherjee, Srinivasaraman Chandrasekaran, Ganapathy Subramanyan E. K., Arul Sendhil

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.

Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

IEEE J. Solid State Circuits, 2012

2011

Self-Calibrating Equalizer for Optimal Jitter Performance Using On-chip Eye Monitoring.

Srinivasaraman Chandrasekaran, Kunal Desai, Arul Sendhil, William Ng

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface.

Navin K. Mishra, Manish Jain, Phuong Le, Sanku Mukherjee, Arul Sendhil, Amir Amirkhany

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011