Arthur H. M. van Roermund

Orcid: 0000-0003-3865-3050

According to our database1, Arthur H. M. van Roermund authored at least 181 papers between 1989 and 2021.

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Bibliography

2021
A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021

2019
A Low-Power Fast Start-Up Crystal Oscillator With an Autonomous Dynamically Adjusted Load.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver.
IEEE J. Solid State Circuits, 2019

2018
A Hybrid Design Automation Tool for SAR ADCs in IoT.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Dimmable integrated CMOS LED driver based on a resonant DC/DC hybrid-switched capacitor converter.
Int. J. Circuit Theory Appl., 2018

A circuit-design-driven tool with a hybrid automation approach for SAR ADCs in IoT.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A 7.1-fJ/Conversion-Step 88-dB SFDR SAR ADC With Energy-Free "Swap To Reset".
IEEE J. Solid State Circuits, 2017

Synthesis-oriented double-loop feedback model.
Int. J. Circuit Theory Appl., 2017

Analogue Frontend Amplifiers for Bio-Potential Measurements Manufactured With a-IGZO TFTs on Flexible Substrate.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

15.3 An a-IGZO asynchronous delta-sigma modulator on foil achieving up to 43dB SNR and 40dB SNDR in 300Hz bandwidth.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 0.9V-VDD sub-nW resistor-less duty-cycled CMOS voltage reference in 65nm for IoT.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Modeling and analysis of the effects of PLL phase noise on FMCW radar performance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A 92.2% peak-efficiency self-resonant hybrid switched-capacitor LED driver in 0.18μm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A106nW 10 b 80 kS/s SAR ADC With Duty-Cycled Reference Generation in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016

A 0.20 mm<sup>2</sup> 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016

A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz.
IEEE J. Solid State Circuits, 2016

A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Higher-order DWA in bandpass delta-sigma modulators and its implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Low-Voltage Chopper-Stabilized Amplifier for Fetal ECG Monitoring With a 1.41 Power Efficiency Factor.
IEEE Trans. Biomed. Circuits Syst., 2015

A 30/35 GHz Dual-Band Transmitter for Phased Arrays in Communication/Radar Applications.
IEEE J. Solid State Circuits, 2015

A design methodology for power-efficient reconfigurable SC ΔΣ modulators.
Int. J. Circuit Theory Appl., 2015

A Background Calibration Technique Based on Limit Cycles for Reconfigurable Sigma Delta Modulators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Automatic filter calibration for bandpass delta-sigma modulators.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A low-power frontend system for fetal ECG monitoring applications.
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

21.2 A 3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

9.6 A 5.3GHz 16b 1.75GS/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Bitstream switching rate based calibration of delta-sigma modulators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A femto-ampere sensitive direct-interface current-input sigma delta ADC for amperometric bio-sensor signal acquisition.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Front End Power Dissipation Minimization and Optimal Transmission Rate for Wireless Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A discrete-time amplifier based on Thin-Film Trans-Capacitors for sensor systems on foil.
Microelectron. J., 2014

Positive-Feedback Level Shifter Logic for Large-Area Electronics.
IEEE J. Solid State Circuits, 2014

A 60-GHz injection locked oscillator for self-demodulation ultra-low power radio in 65-nm CMOS.
Proceedings of the 21st IEEE Symposium on Communications and Vehicular Technology in the Benelux, 2014

11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

30.4 A 13.56MHz RFID tag with active envelope detection in an organic complementary TFT technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A multiple-channel frontend system with current reuse for fetal monitoring applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Limit cycle counting based smart background calibration of continuous time sigma delta ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 60-GHz energy harvesting module with on-chip antenna and switch for co-integration with ULP radios in 65-nm CMOS with fully wireless mm-wave power transfer measurement.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A scalable baseband phase shifter with 12 GHz I/Q Mixers in 40-nm CMOS for 60 GHz applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A novel timing-error based approach for high speed highly linear Mixing-DAC architectures.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Implications of I/Q Imbalance, Phase Noise and Noise Figure for SNR and BER of FSK Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Mixer-First FSK Receiver With Automatic Frequency Control for Body Area Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 155 µW 88-dB DR Discrete-Time ΔΣ Modulator for Digital Hearing Aids Exploiting a Summing SAR ADC Quantizer.
IEEE Trans. Biomed. Circuits Syst., 2013

A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step.
IEEE J. Solid State Circuits, 2013

Low frequency dithering technique for linearization of voltage mode class-D amplifiers.
Proceedings of the 2013 IEEE Radio and Wireless Symposium, 2013

A discrete-time amplifier based on Thin-Film Trans-Capacitors for organic sensor frontends.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

An organic VCO-based ADC for quasi-static signals achieving 1LSB INL at 6b resolution.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 4b ADC manufactured in a fully-printed organic complementary technology including resistors.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A low-power noise scalable instrumentation amplifier for fetal monitoring applications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 60-GHz rectenna for monolithic wireless sensor tags.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

System analysis and energy model for radio-triggered battery-less monolithic wireless sensor receiver.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Analog to digital converters on plastic foils.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

A 1-V 99-to-75dB SNDR, 256Hz-16kHz bandwidth, 8.6-to-39µW reconfigurable SC ΔΣ Modulator for autonomous biomedical applications.
Proceedings of the ESSCIRC 2013, 2013

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals.
Proceedings of the ESSCIRC 2013, 2013

A novel output transformer based highly linear RF-DAC architecture.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A 430nW 64nV/vHz current-reuse telescopic amplifier for neural recording applications.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012
A Power-Optimal Design Methodology for High-Resolution Low-Bandwidth SC ΔΣ Modulators.
IEEE Trans. Instrum. Meas., 2012

An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 60GHz fully integrated power amplifier using a distributed ring transformer in CMOS 65nm.
Proceedings of the 19th IEEE Symposium on Communications and Vehicular Technology in the Benelux, 2012

A broadband frontend design for UHF RFID tag.
Proceedings of the 19th IEEE Symposium on Communications and Vehicular Technology in the Benelux, 2012

A 107GHz LNA in 65nm CMOS with inductive neutralization and slow-wave transmission lines.
Proceedings of the 19th IEEE Symposium on Communications and Vehicular Technology in the Benelux, 2012

A 6b 10MS/s current-steering DAC manufactured with amorphous Gallium-Indium-Zinc-Oxide TFTs achieving SFDR > 30dB up to 300kHz.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A synchronous rail-to-rail latched comparator based on double-gate organic thin-film-transistors.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Ultra-low power FSK receiver for body area networks with automatic frequency control.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Design of analog and digital building blocks in a fully printed complementary organic technology.
Proceedings of the 38th European Solid-State Circuit conference, 2012

A 155µW 88-dB DR discrete-time ΔΣ modulator for digital hearing aid applications.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

2011
System Level Receiver Design for Minimum Sensitivity to Process Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Statistical Analysis of Self-Oscillating Power Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping.
IEEE J. Solid State Circuits, 2011

Requirement driven low-power LC and ring oscillator design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Timing error measurement for highly linear wideband Digital to Analog Converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A novel temperature and disturbance insensitive DAC calibration method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A tunable transconductor for analog amplification and filtering based on double-gate organic TFTs.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Adaptive Impedance-Matching Techniques for Controlling <i>L</i> Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems.
IEEE J. Solid State Circuits, 2010

Extended modelling for time-encoding converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Analytical passive mixer power gain models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An EFOM for cross-layer optimization towards low-power and high-performance wireless networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 70 GHz 10.2 mW self-demodulator for OOK modulation in 65-nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 40-GHz phase-locked loop front-end for 60-GHz transceivers in 65nm CMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Analog calibration of channel mismatches in time-interleaved ADCs.
Int. J. Circuit Theory Appl., 2009

Smart Front-Ends, from Vision to Design.
IEICE Trans. Electron., 2009

A 0.75V 325µW 40dB-SFDR frequency-hopping synthesizer for wireless sensor networks in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Analytical Models for the Wake-Up Receiver Power Budget for Wireless Sensor Networks.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

2008
Receiver Front-End Circuits for Future Generations of Wireless Communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A GSM/EDGE/WCDMA Adaptive Series-LC Matching Network Using RF-MEMS Switches.
IEEE J. Solid State Circuits, 2008

Predictive timing error calibration technique for RF current-steering DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 60GHz digitally controlled phase shifter in CMOS.
Proceedings of the ESSCIRC 2008, 2008

A 1.2V receiver front-end for multi-standard wireless applications in 65 nm CMOS LP.
Proceedings of the ESSCIRC 2008, 2008

A flexible 12-bit self-calibrated quad-core current-steering DAC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 1 mA Ultra-Low-Power FHSS TX Front-End Utilizing Direct Modulation With Digital Pre-Distortion.
IEEE J. Solid State Circuits, 2007

Power Amplifier Protection by Adaptive Output Power Control.
IEEE J. Solid State Circuits, 2007

Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption.
Integr., 2007

A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Parallel current-steering D/A Converters for Flexibility and Smartness.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analysis of Open Loop Track-and-Hold Circuits.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A broadband, inductorless LNA for multi-standard aplications.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Smart, flexible, and future-proof data converters.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Sigma-delta modulators operating at a limit cycle.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer.
IEEE J. Solid State Circuits, 2006

A Frequency Offset Recovery Algorithm for Crystal-Less Transmitters.
Proceedings of the IEEE 17th International Symposium on Personal, 2006

DDL-based calibration techniques for timing errors in current-steering DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A binary-to-thermometer decoder with built-in redundancy for improved DAC yield.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An ultra-low power predistortion-based FHSS transmitter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Digital post-correction of front-end track-and-hold circuits in ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Adaptive methods to preserve power amplifier linearity under antenna mismatch conditions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A low-voltage folded-switching mixer in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2005

A CMOS V-I converter with 75-dB SFDR and 360-μW power consumption.
IEEE J. Solid State Circuits, 2005

A flexible ADC approach for mixed-signal SoC platforms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Smart AD and DA converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A start-up calibration method for generic current-steering D/A converters with optimal area solution.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Accuracy limitations of pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Digital self-correction of time-interleaved ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An on-chip self-calibration method for current mismatch in D/A converters.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

A 28.5 GHz monolithic cascode LNA with 70GHz f<sub>T</sub> SiGe HBTs.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Explicit design equations for class-E power amplifiers with small DC-feed inductance.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A FSK demodulator comparison for ultra-low power, low data-rate wireless links in ISM bands.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
A continuous-time ΣΔ ADC with increased immunity to interferers.
IEEE J. Solid State Circuits, 2004

A DECT/Bluetooth multi-standard front-end with adaptive image rejection in 0.18µm CMOS.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low voltage, low power folded-switching mixer with current-reuse in 0.18µm CMOS.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Fully-integrated DECT/Bluetooth multi-band LNA in 0.18µm CMOS.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Intermodulation products in the EER technique applied to class-E amplifiers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

CMOS V-I converter with 75dB SFDR and 360μW power consumption.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Modelling conditions for nanoelectronics, and elaboration for set circuits.
Int. J. Circuit Theory Appl., 2003

Mixer topology selection for a 1.8 - 2.5 GHz multi-standard front-end in 0.18µm CMOS.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

On the feasibility of application of class E RF power amplifiers in UMTS.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Mismatch-based timing errors in current steering DACs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A surface-mounted RF IC technology demonstrated with a 10 GHz LC oscillator with copper coils.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A 3.3-mW ΣΔ modulator for UMTS in 0.18-μm CMOS with 70-dB dynamic range in 2-MHz bandwidth.
IEEE J. Solid State Circuits, 2002

Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator.
IEEE J. Solid State Circuits, 2002

A 9.8-11.5-GHz quadrature ring oscillator for optical receivers.
IEEE J. Solid State Circuits, 2002

A general analysis on the timing jitter in D/A converters.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis of an 1.8 - 2.5 GHz multi-standard high image-reject front-end.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
Spike correlation based learning for unsupervised neural lattice structures.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Terminal dynamics approach to cellular neural networks.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

On the stability of high order Sigma-Delta modulators.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

D/A conversion: amplitude and time error mapping optimization.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
A 10.7-MHz CMOS SC radio IF filter using orthogonal hardware modulation.
IEEE J. Solid State Circuits, 2000

Design philosophy for nanoelectronic systems, from SETs to neural nets.
Int. J. Circuit Theory Appl., 2000

From nanotechnology to nanoelectronic systems, from SETs to neural nets.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Ultra-low standby-currents for deep sub-micron VLSI CMOS circuits: smart series switch.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
An Artificial Dendrite Using Active Channels.
Proceedings of the Engineering Applications of Bio-Inspired Artificial Neural Networks, 1999

The linear time-varying approach applied to the design of a negative-feedback class-B output amplifier.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A low-voltage translinear second-order quadrature oscillator.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

The linear time-varying approach applied to a first-order dynamic translinear filter.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Analysis of noise in higher-order translinear filters.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Wireless optical PPM telemetry and the influence of lighting flicker.
IEEE Trans. Instrum. Meas., 1998

A wide-tunable translinear second-order oscillator.
IEEE J. Solid State Circuits, 1998

A 300°C dynamic-feedback instrumentation amplifier.
IEEE J. Solid State Circuits, 1998

An ultra-low-power, low-voltage electronic audio delay line for use in hearing aids.
IEEE J. Solid State Circuits, 1998

1997
A low-voltage ultra-low-power translinear integrator for audio filter applications.
IEEE J. Solid State Circuits, 1997

An RMS-DC converter based on the dynamic translinear principle.
IEEE J. Solid State Circuits, 1997

A reduced-area low-power low-voltage single-ended differential pair.
IEEE J. Solid State Circuits, 1997

Low-power MOS integrated filter with transconductors with spoilt current sources.
IEEE J. Solid State Circuits, 1997

1995
A low-cost multichannel optical transmission system for video signals.
IEEE Trans. Commun., 1995

1994
A low-voltage low-power fully-integratable automatic gain control for hearing instruments.
IEEE J. Solid State Circuits, August, 1994

Low-Voltage Low-Power Fully-Integratable Automatic Gain Controls.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Partitioning-based Method to Determine the Uniqueness of the DC Operating Points of Transistor Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Charge Pump for optimal dynamic range filters.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Design of Optimal Dynamic Range Integrated Mixer-Filter Systems.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Design of a processing board for a programmable multi-VSP system.
J. VLSI Signal Process., 1993

1989
A general-purpose video signal processor: architecture and programming.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

A programmable video signal processor.
Proceedings of the IEEE International Conference on Acoustics, 1989


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