Arthur Abnous

According to our database, Arthur Abnous authored at least 7 papers between 1991 and 2001.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2001

Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System.

Marlene Wan, Hui Zhang, George Varghese, Martin Benes, Arthur Abnous, Vandana Prabhu, Jan M. Rabaey

J. VLSI Signal Process., 2001

2000

A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing.

Hui Zhang, Vandana Prabhu, George Varghese, Marlene Wan, Martin Benes, Arthur Abnous, Jan M. Rabaey

IEEE J. Solid State Circuits, 2000

1998

Evaluation of a Low-Power Reconfigurable DSP Architecture.

Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marlene Wan, Jan M. Rabaey

Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

1994

Pipelining and Bypassing in a VLIW Processor.

Arthur Abnous, Nader Bagherzadeh

IEEE Trans. Parallel Distributed Syst., 1994

1992

Design and implementation of the 'Tiny RISC' microprocessor.

Arthur Abnous, Christopher Christensen, Jeffrey Gray, John Lenell, Andrew Naylor, Nader Bagherzadeh

Microprocess. Microsystems, 1992

1991

Special Features of a VLIW Architecture.

Arthur Abnous, Nader Bagherzadeh

Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

A Percolation Based VLIW Architecture.

Arthur Abnous, Roni Potasman, Nader Bagherzadeh, Alexandru Nicolau

Proceedings of the International Conference on Parallel Processing, 1991