Arnold Weinberger

According to our database1, Arnold Weinberger authored at least 14 papers between 1954 and 1991.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1984, "For contributions to the theory of computer arithmetic logic, and to the layout of large-scale integrated circuits.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1991
An adder design optimized for DCS logic.
IBM J. Res. Dev., 1991

1979
High-Speed Programmable Logic Array Adders.
IBM J. Res. Dev., 1979

1978
Parallel adders using standard plas.
Proceedings of the 4th IEEE Symposium on Computer Arithmetic, 1978

1975
High-speed zero-sum detection.
Proceedings of the 3rd IEEE Symposium on Computer Arithmetic, 1975

1971
High Speed Decimal Addition.
IEEE Trans. Computers, 1971

1961
Using Digital Computers in the Design and Maintenance of New Computers.
IRE Trans. Electron. Comput., 1961

1959
PILOT - A New Multiple Computer System.
J. ACM, 1959

1958
PILOT, the NBS multicomputer system.
Proceedings of the Papers and discussions presented at the 1958 eastern joint computer conference: Modern computers: objectives, 1958

1957
Symbolic Designations for Electrical Connections.
J. ACM, 1957

Formal Procedures for Connecting Terminals with a Minimum Total Wire Length.
J. ACM, 1957

Organizing a network of computers to meet deadlines.
Proceedings of the Papers and discussions presented at the 1957 eastern joint computer conference: Computers with deadlines to meet, 1957

1956
A One-Microsecond Adder Using One-Megacycle Circuitry.
IRE Trans. Electron. Comput., 1956

The logical design of a 1-microsecond parallel adder using 1-megacycle circuitry.
Proceedings of the Papers presented at the 1956 joint ACM-AIEE-IRE western computer conference, 1956

1954
System design of the SEAC and DYSEAC.
Trans. I R E Prof. Group Electron. Comput., 1954


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