Arnaud Régnier

According to our database1, Arnaud Régnier authored at least 18 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
40nm SONOS Embedded Select in Trench Memory.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

Notched gate MOSFET for capacitance reduction in RF SOI technology.
Proceedings of the 2023 IEEE International Conference on Design, 2023

2022
Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Schmitt trigger to benchmark the performance of a new zero-cost transistor.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Hot Electron Source Side Injection Comprehension in 40nm eSTM™.
Proceedings of the IEEE International Memory Workshop, 2021

Simulation of state of the art EEPROM programming window closure during endurance degradation.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020
AC stress reliability study of a new high voltage transistor for logic memory circuits.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2018
Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction.
Microelectron. Reliab., 2018

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2015
Layout optimizations to decrease internal power and area in digital CMOS standard cells.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015

2014
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2012
Effects of 1064 nm laser on MOS capacitor.
Microelectron. Reliab., 2012

Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability.
J. Low Power Electron., 2012

2010
Leakage paths identification in NVM using biased data retention.
Microelectron. Reliab., 2010

2008
Dynamic stress method for accurate NVM oxide robustness evaluation for automotive applications.
Microelectron. Reliab., 2008

2006
MM11 based flash memory cell model including characterization procedure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006


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