Arnaud Poittevin
According to our database1,
Arnaud Poittevin
authored at least 5 papers
between 2020 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
2020
2021
2022
0
1
2
3
1
2
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
2020
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR, 2020
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.
Proceedings of the VLSI-SoC: Design Trends, 2020