Armita Ardeshiricham
According to our database1,
Armita Ardeshiricham
authored at least 12 papers
between 2016 and 2022.
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Bibliography
2022
Behavioral Synthesis for Hardware Security, 2022
2020
2019
VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive Information Flow Properties.
Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019
2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Examining the consequences of high-level synthesis optimizations on power side-channel.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017
Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Register transfer level information flow tracking for provably secure hardware design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016
Imprecise security: quality and complexity tradeoffs for hardware information flow tracking.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016