Armin Tajalli

Yen-Cheng Kuan

IEEE Trans. Circuits Syst. II Express Briefs, August, 2024

Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers.

[BibT_eX]

[DOI]

Behdad Jamadi

IEEE Trans. Very Large Scale Integr. Syst., July, 2024

Effect of Parameter Drift on the Accuracy of Analog CNN Accelerators.

[BibT_eX]

[DOI]

Michael Keyser

Farzad T. Ordubadi

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Speed-Noise-Power Trade-Offs in Design of Scaled FET Circuits Using $\mathrm{C}/\mathrm{I}_{\mathrm{D}}$ Methodology.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

Hadamard Multi-Tone Signaling in Multi-Wire Pulse Amplitude Modulation for Next Generation Wireline Communication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

Noise-Aware FET Circuit Design Based on C/ID-Invariant.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

Extending C/ID Methodology for Optimal Implementation of Single-Stage Discrete-Time Amplifiers.

[BibT_eX]

[DOI]

Sakthidasan Kalidasan

Proceedings of the 19th International Conference on Synthesis, 2023

Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology.

[BibT_eX]

[DOI]

Behdad Jamadi

Fariborz T. Ordubadi

Proceedings of the 19th International Conference on Synthesis, 2023

A VCO Linearization Technique Using Dual-VCO and Interpolation for Time-Based ADCs.

[BibT_eX]

[DOI]

Shea Smith

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Computational Efficiency of Circuit Design and Optimization Algorithms: A Comparative Study.

[BibT_eX]

[DOI]

Alec Adair

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation Linearization.

[BibT_eX]

[DOI]

Mau-Chung Frank Chang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022

Systematic Design of Loop Circuit Topologies Using C/IDS Methodology.

[BibT_eX]

[DOI]

Jacob Atkinson

Anthony Bailey

IEEE Trans. Very Large Scale Integr. Syst., 2022

Balanced Circuit Topologies and Their Applications in Data Movement.

[BibT_eX]

[DOI]

Amin Shokrollahi

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2021

A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/IDS Methodology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Controllable KVCO Ring VCO Topology.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Optimal PAM Order for Wireline Communication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors.

[BibT_eX]

[DOI]

Mohammad Taherzadeh-Sani

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

An ULP Self-Supplied Brain Interface Circuit.

[BibT_eX]

[DOI]

Massood Tabib-Azar

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector.

[BibT_eX]

[DOI]

Behrouz Farhang-Boroujeny

Proceedings of the VLSI-SoC: Design Trends, 2020

Energy and Area Efficient Mixed-Mode MCMC MIMO Detector.

[BibT_eX]

[DOI]

Behrouz Farhang-Boroujeny

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Digitally-Assisted Peak Detector for Periodic Signal.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Power System Emulator Based on PLL Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS.

[BibT_eX]

[DOI]

Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

CMOS Amplifier Design Based on Extended $g_{m}/I_{D}$ Methodology.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Spectrum-Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2018

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

2017

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016

A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2015

A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2015

10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces.

[BibT_eX]

[DOI]

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

2012

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011

Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Design trade-offs in ultra-low-power CMOS and STSCL digital systems.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Leakage Current Reduction Using Subthreshold Source-Coupled Logic.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits.

[BibT_eX]

[DOI]

Massimo Alioto

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP.

[BibT_eX]

[DOI]

Elizabeth J. Brauer

Microelectron. J., 2009

A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance.

[BibT_eX]

[DOI]

Pooyan Sakian

Mohsen Saffari

IET Circuits Devices Syst., 2008

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Improving the power-delay product in SCL circuits using source follower output stage.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2007

A Power Optimized Base-Band Circuitry for the Low-IF Receivers.

[BibT_eX]

[DOI]

Ramin Zanbaghi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept.

[BibT_eX]

[DOI]

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 1/4 rate linear phase detector for PLL-based CDR circuits.

[BibT_eX]

[DOI]

Mohsen Saffari

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A technique to suppress tail current flicker noise in CMOS LC VCOs.

[BibT_eX]

[DOI]

Saeed Saeedi

Saeid Mehrmanesh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

A low-power, multichannel gated oscillator-based CDR for short-haul applications.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer.

[BibT_eX]

[DOI]

Pooya Torkzadeh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops.

[BibT_eX]

[DOI]

Pooya Torkzadeh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 31st European Solid-State Circuits Conference, 2005

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

A fractional delay-locked loop for on chip clock generation applications.

[BibT_eX]

[DOI]

Pooya Torkzadeh

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A duty cycle control circuit for high speed applications.

[BibT_eX]

[DOI]

Saeid Mehrmanesh

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Design and optimization of a high PSRR CMOS bandgap voltage reference.

[BibT_eX]

[DOI]

Abbas Khodaverdi

Farzad Sahandi Esfanjani

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Structured design of an integrated subscriber line interface system and circuit.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A compact biquadratic gm-C filter structure for low-voltage and high frequency applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A compact, low power, fully integrated clock frequency doubler.

[BibT_eX]

[DOI]

Abbas Khodaverdi

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002

A low-power subscriber line interface circuit in a high-voltage CMOS technology.

[BibT_eX]

[DOI]

Mohammad B. Vahidfar

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000

A 1.5-V supply, video range frequency, Gm-C filter.

[BibT_eX]

[DOI]