Armin M. Reith

According to our database, Armin M. Reith authored at least 2 papers between 1999 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2000

A 7F² cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.

Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman

IEEE J. Solid State Circuits, 2000

1999

A 390-mm², 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture.

Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman

IEEE J. Solid State Circuits, 1999