Arman Roohi

Orcid: 0000-0002-0900-8768

According to our database1, Arman Roohi authored at least 69 papers between 2015 and 2024.

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Bibliography

2024
PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks.
IEEE Trans. Emerg. Top. Comput., 2024

HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI.
CoRR, 2024

DECO: Dynamic Energy-aware Compression and Optimization for In-Memory Neural Networks.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

ResSen: Imager Privacy Enhancement Through Residue Arithmetic Processing in Sensors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Energy-Efficient Near-Sensor Event Detector Based on Multilevel Ga2O3 RRAM.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Resource-Efficient Adaptive-Network Inference Framework with Knowledge Distillation-Based Unified Learning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

RACSen: Residue Arithmetic and Chaotic Processing in Sensors to Enhance CMOS Imager Security.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

DRAM-Locker: A General-Purpose DRAM Protection Mechanism Against Adversarial DNN Weight Attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Design and evaluation of ultra-fast 8-bit approximate multipliers using novel multicolumn inexact compressors.
Int. J. Circuit Theory Appl., July, 2023

AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

PISA: A Non-Volatile Processing-in-Sensor Accelerator for Imaging Systems.
IEEE Trans. Emerg. Top. Comput., 2023

Enabling Normally-off In-Situ Computing with a Magneto-Electric FET-based SRAM Design.
CoRR, 2023

Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

NeSe: Near-Sensor Event-Driven Scheme for Low Power Energy Harvesting Sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Deep Mapper: A Multi-Channel Single-Cycle Near-Sensor DNN Accelerator.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023

EnCoDe: Enhancing Compressed Deep Learning Models Through Feature - - - Distillation and Informative Sample Selection.
Proceedings of the International Conference on Machine Learning and Applications, 2023

SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

P-PIM: A Parallel Processing-in-DRAM Framework Enabling Row Hammer Protection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
HARDeNN: Hardware-assisted attack-resilient deep neural network architectures.
Microprocess. Microsystems, November, 2022

PISA: A Binary-Weight Processing-In-Sensor Accelerator for Edge Image Processing.
CoRR, 2022

LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking.
IEEE Comput. Archit. Lett., 2022

Design and Evaluation of a Robust Power-Efficient Ternary SRAM Cell.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

ReFACE: Efficient Design Methodology for Acceleration of Digital Filter Implementations.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Integrated Sensing and Computing using Energy-Efficient Magnetic Synapses.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

FlexiDRAM: A Flexible in-DRAM Framework to Enable Parallel General-Purpose Computation.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

SCiMA: A Generic Single-Cycle Compute-in-Memory Acceleration Scheme for Matrix Computations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

semiMul: Floating-Point Free Implementations for Efficient and Accurate Neural Network Training.
Proceedings of the 21st IEEE International Conference on Machine Learning and Applications, 2022

Enabling Efficient Training of Convolutional Neural Networks for Histopathology Images.
Proceedings of the Image Analysis and Processing. ICIAP 2022 Workshops, 2022

TizBin: A Low-Power Image Sensor with Event and Object Detection Using Efficient Processing-in-Pixel Schemes.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

ReD-LUT: Reconfigurable In-DRAM LUTs Enabling Massive Parallel Computation.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Efficient Targeted Bit-Flip Attack Against the Local Binary Pattern Network.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Toward a Behavioral-Level End-to-End Framework for Silicon Photonics Accelerators.
Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022

Work-in-Progress: A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM.
Proceedings of the International Conference on Compilers, 2022

2021
Ultra-Fast, High-Performance 8x8 Approximate Multipliers by a New Multicolumn 3, 3: 2 Inexact Compressor and its Derivatives.
CoRR, 2021

RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural Network.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
ApGAN: Approximate GAN for Robust Low Energy Learning From Imprecise Components.
IEEE Trans. Computers, 2020

Entropy-Based Modeling for Estimating Soft Errors Impact on Binarized Neural Network Inference.
CoRR, 2020

Fiji-FIN: A Fault Injection Framework on Quantized Neural Network Inference Accelerator.
Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020

Normally-off computing design methodology using spintronics: from device to architectures.
Proceedings of the 11th International Green and Sustainable Computing Workshops, 2020

SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience.
CoRR, 2019

IRC Cross-Layer Design Exploration of Intermittent Robust Computation Units for IoTs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018
A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency.
IEEE Trans. Emerg. Top. Comput., 2018

NV-Clustering: Normally-Off Computing Using Non-Volatile Datapaths.
IEEE Trans. Computers, 2018

Synthesis of normally-off boolean circuits: An evolutionary optimization approach utilizing spintronic devices.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath Design.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Towards ultra-efficient QCA reversible circuits.
Microprocess. Microsystems, 2017

Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing.
IET Circuits Devices Syst., 2017

Secure intermittent-robust computation for energy harvesting device security and outage resilience.
Proceedings of the 2017 IEEE SmartWorld, 2017

Heterogeneous Technology Configurable Fabrics for Field-Programmable Co-Design of CMOS and Spin-Based Devices.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016
Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks.
IEEE Trans. Computers, 2016

2015
Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder.
Microelectron. J., 2015

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops.
J. Circuits Syst. Comput., 2015

Modeling an Improved Modified Type in Metallic Quantum-Dot Fixed Cell for Nano Structure Implementation.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Reactive rejuvenation of CMOS logic paths using self-activating voltage domains.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015


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