Arkadiy Morgenshtein

According to our database, Arkadiy Morgenshtein authored at least 21 papers between 2002 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2017

Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms.

Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son

IEEE Des. Test, 2017

2016

Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification.

Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Comparative study of test generation methods for simulation accelerators.

Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Full-Swing Gate Diffusion Input logic - Case-study of low-power CLA adder design.

Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish

Integr., 2014

Effective post-silicon failure localization using dynamic program slicing.

Ophir Friedler, Wisam Kadry, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2010

Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696].

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2010

Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2010

2008

Timing optimization in logic with interconnect.

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny

Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Parallel vs. serial on-chip communication.

Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar

Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

2006

Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.

Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2006

2005

Low-leakage repeaters for NoC interconnects.

Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Asynchronous gate-diffusion-input (GDI) circuits.

Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar

IEEE Trans. Very Large Scale Integr. Syst., 2004

Comparative analysis of serial vs parallel links in NoC.

Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

An efficient implementation of D-Flip-Flop using the GDI technique.

Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

ISFET CMOS compatible design and encapsulation challenges.

Liby Sudakov-Boreysha, Arkadiy Morgenshtein, Uri Dinnar, Yael Nemirovsky

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Micro-modem - reliability solution for NoC communications.

Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization.

Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Automatic hardware-efficient SoC integration by QoS network on chip.

Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003

Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.

Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny

Proceedings of the IFIP VLSI-SoC 2003, 2003

2002

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits.

Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner

IEEE Trans. Very Large Scale Integr. Syst., 2002

Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization.

Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002