Arjun Ramaswami Palaniappan

According to our database, Arjun Ramaswami Palaniappan authored at least 5 papers between 2015 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

A TDC-less all-digital phase locked loop for medical implant applications.

Arjun Ramaswami Palaniappan, Liter Siek

Microprocess. Microsystems, 2019

A 0.6 V, 1.74 ps Resolution Capacitively Boosted Time-to-Digital Converter in 180 nm CMOS.

Arjun Ramaswami Palaniappan, Liter Siek

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A 0.0186 mm², 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants.

Arjun Ramaswami Palaniappan, Liter Siek

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

2016

Review of pulse generators for gated ring oscillator based Time-to-Digital converters.

Jian Sen Teh, Arjun Ramaswami Palaniappan, Liter Siek, Yuanjin Zheng

Proceedings of the International Symposium on Integrated Circuits, 2016

2015

A higher order curvature corrected 2 ppm/°C CMOS voltage reference circuit.

Arjun Ramaswami Palaniappan, Dominic Maurath, Felix Kalathiparambil, Liter Siek

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015