Arjan J. van Genderen

According to our database1, Arjan J. van Genderen authored at least 9 papers between 1989 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2009
Can SG-FET Replace FET in Sleep Mode Circuits?
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

1996
Fast Computation of Substrate Resistances in Large Circuits.
Proceedings of the 1996 European Design and Test Conference, 1996

Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Extraction of circuit models for substrate cross-talk.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Network initialization in a switch-level simulator.
Proceedings of the 1995 European Design and Test Conference, 1995

Delayed Frontal Solution for Finite-Element Based Resistance Extraction.
Proceedings of the 32st Conference on Design Automation, 1995

1993
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1989
An Efficient Finite Element Method for Submicron IC Capacitance Extraction.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989


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