Aritra Hazra
Orcid: 0000-0003-2076-3577
According to our database1,
Aritra Hazra
authored at least 59 papers
between 2008 and 2024.
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Bibliography
2024
IEEE Trans. Inf. Forensics Secur., 2024
DiffClone: Enhanced Behaviour Cloning in Robotics with Diffusion-Driven Policy Learning.
CoRR, 2024
PURSE: Property Ordering Using Runtime Statistics for Efficient Multi - Property Verification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
CoVerPlan: A Comprehensive Verification Planning Framework Leveraging PSS Specifications.
ACM Trans. Design Autom. Electr. Syst., January, 2023
Explainable Decision Tree-Based Screening of Cognitive Impairment Leveraging Minimal Neuropsychological Tests.
Proceedings of the Pattern Recognition and Machine Intelligence, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Physically Related Functions: Exploiting Related Inputs of PUFs for Authenticated-Key Exchange.
IEEE Trans. Inf. Forensics Secur., 2022
The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IACR Cryptol. ePrint Arch., 2022
Formal Methods for Characterization and Analysis of Quality Specifications in Component-based Systems.
CoRR, 2022
CoRR, 2022
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
2021
ACM Trans. Design Autom. Electr. Syst., 2021
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
IEEE Embed. Syst. Lett., 2021
IEEE Embed. Syst. Lett., 2021
Detecting Adversaries, yet Faltering to Noise? Leveraging Conditional Variational AutoEncoders for Adversary Detection in the Presence of Noisy Images.
CoRR, 2021
Methodology for Biasing Random Simulation for Rapid Coverage of Corner Cases in AMS Designs.
CoRR, 2021
An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
SACReD: An Attack Framework on SAC Resistant Delay-PUFs leveraging Bias and Reliability Factors.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
FEDS: Comprehensive Fault Attack Exploitability Detection for Software Implementations of Block Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Early-Stage Resource Estimation from Functional Reliability Specification in Embedded Cyber-Physical Systems.
CoRR, 2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
PUF-G: A CAD Framework for Automated Assessment of Provable Learnability from Formal PUF Representations.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Formal Analysis of PUF Instances Leveraging Correlation-Spectra in Boolean Functions.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019
2018
ACM Trans. Design Autom. Electr. Syst., 2018
CoRR, 2018
Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
2017
RELSPEC: a framework for reliability aware design of component based embedded systems.
Des. Autom. Embed. Syst., 2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
J. Appl. Log., 2016
Synthesis of scheduler automata guaranteeing stability and reliability of embedded control systems.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
2015
Proceedings of the 28th International Conference on VLSI Design, 2015
2014
Proceedings of the 2014 IEEE International Conference on Control System, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Embed. Syst. Lett., 2013
Formal Methods for Early Analysis of Functional Reliability in Component-Based Embedded Applications.
IEEE Embed. Syst. Lett., 2013
Handling fault detection latencies in automata-based scheduling for embedded control software.
Proceedings of the 2013 IEEE International Symposium on Computer-Aided Control System Design, 2013
2012
J. Low Power Electron., 2012
J. Electron. Test., 2012
Reliability annotations to formal specifications of context-sensitive safety properties in embedded systems.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012
Formal methods for coverage analysis of architectural power states in power-managed designs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Proceedings of the International Symposium on Electronic System Design, 2011
2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent.
Proceedings of the 47th Design Automation Conference, 2010
2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008