Aristides Efthymiou

According to our database, Aristides Efthymiou authored at least 22 papers between 1995 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Exploring the Design Space of 32x32 Approximate Reduced Complexity Wallace Multipliers.

Ioannis Rizos, Georgios Papatheodorou, Aristides Efthymiou

Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024

Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems.

Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas

Proceedings of the International Conference on Artificial Intelligence in Information and Communication , 2024

2022

Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles.

Christoforos Papaioannou, Marina E. Plissiti, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas

Proceedings of the 10th IEEE International Black Sea Conference on Communications and Networking, 2022

2021

An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems.

Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas

Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2021

2013

An error tolerant CAM with nand match-line organization.

Aristides Efthymiou

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2010

Initialization-Based Test Pattern Generation for Asynchronous Circuits.

Aristides Efthymiou

IEEE Trans. Very Large Scale Integr. Syst., 2010

Optimising Self-Timed FPGA Circuits.

Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2008

A Partial Scan Based Test Generation for Asynchronous Circuits.

Dilip P. Vasudevan, Aristides Efthymiou

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits.

Aristides Efthymiou

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Synthetic Trace-Driven Simulation of Cache Memory.

Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou

Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2005

Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.

Aristides Efthymiou, John Bainbridge, Douglas A. Edwards

IEEE Trans. Very Large Scale Integr. Syst., 2005

Fast, Parallel Two-Rail Code Checker with Enhanced Testability.

Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A Low-Power Processor Architecture Optimized forWireless Devices.

Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

A CAM with mixed serial-parallel comparison for use in low energy caches.

Aristides Efthymiou, Jim D. Garside

IEEE Trans. Very Large Scale Integr. Syst., 2004

Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.

Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards

Proceedings of the 2004 Design, 2004

Adding Testability to an Asynchronous Interconnect for GALS SoC.

Aristides Efthymiou, John Bainbridge, Douglas A. Edwards

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.

Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury

Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003

Adaptive Pipeline Structures fo Speculation Control.

Aristides Efthymiou, Jim D. Garside

Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002

An adaptive serial-parallel CAM architecture for low-power cache blocks.

Aristides Efthymiou, Jim D. Garside

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Adaptive Pipeline Depth Control for Processor Power-Management.

Aristides Efthymiou, Jim D. Garside

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Power Management in the Amulet Microprocessors.

Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple

IEEE Des. Test Comput., 2001

1995

Pipelined Memory Shared Buffer for VLSI Switches.

Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou

Proceedings of the ACM SIGCOMM 1995 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, Cambridge, MA, USA, August 28, 1995