Arish Sateesan

According to our database, Arish Sateesan authored at least 14 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

SPArch: A Hardware-oriented Sketch-based Architecture for High-speed Network Flow Measurements.

Arish Sateesan, Jo Vliegen, Simon Scherrer, Hsu-Chun Hsiao, Adrian Perrig, Nele Mentens

ACM Trans. Priv. Secur., November, 2024

A Genetic Programming approach for hardware-oriented hash functions for network security applications.

Mujtaba Hassan, Arish Sateesan, Jo Vliegen, Stjepan Picek, Nele Mentens

Appl. Soft Comput., 2024

2023

Optimized algorithms and architectures for fast non-cryptographic hash functions in hardware.

Arish Sateesan, Jelle Biesmans, Thomas Claesen, Jo Vliegen, Nele Mentens

Microprocess. Microsystems, April, 2023

ALBUS: a Probabilistic Monitoring Algorithm to Counter Burst-Flood Attacks.

Simon Scherrer, Jo Vliegen, Arish Sateesan, Hsu-Chun Hsiao, Nele Mentens, Adrian Perrig

Proceedings of the 42nd International Symposium on Reliable Distributed Systems, 2023

Evolving Non-cryptographic Hash Functions Using Genetic Programming for High-speed Lookups in Network Security Applications.

Mujtaba Hassan, Arish Sateesan, Jo Vliegen, Stjepan Picek, Nele Mentens

Proceedings of the Applications of Evolutionary Computation - 26th European Conference, 2023

2022

Hardware-oriented optimization of Bloom filter algorithms and architectures for ultra-high-speed lookups in network applications.

Arish Sateesan, Jo Vliegen, Joan Daemen, Nele Mentens

Microprocess. Microsystems, September, 2022

An Analysis of the Hardware-Friendliness of AMQ Data Structures for Network Security.

Arish Sateesan, Jo Vliegen, Nele Mentens

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2022

2021

A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs.

Arish Sateesan, Sharad Sinha, Smitha K. G., A. P. Vinod

Neural Process. Lett., 2021

Low-Rate Overuse Flow Tracer (LOFT): An Efficient and Scalable Algorithm for Detecting Overuse Flows.

Simon Scherrer, Che-Yu Wu, Yu-Hsi Chiang, Benjamin Rothenberger, Daniele Enrico Asoni, Arish Sateesan, Jo Vliegen, Nele Mentens, Hsu-Chun Hsiao, Adrian Perrig

Proceedings of the 40th International Symposium on Reliable Distributed Systems, 2021

SoK - Network Intrusion Detection on FPGA.

Laurens Le Jeune, Arish Sateesan, Md Masoom Rabbani, Toon Goedemé, Jo Vliegen, Nele Mentens

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2021

Speed Records in Network Flow Measurement on FPGA.

Arish Sateesan, Jo Vliegen, Simon Scherrer, Hsu-Chun Hsiao, Adrian Perrig, Nele Mentens

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Novel Non-cryptographic Hash Functions for Networking and Security Applications on FPGA.

Thomas Claesen, Arish Sateesan, Jo Vliegen, Nele Mentens

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020

DASH: Design Automation for Synthesis and Hardware Generation for CNN.

Arish Sateesan, Sharad Sinha, Smitha K. G.

Proceedings of the International Conference on Field-Programmable Technology, 2020

Novel Bloom filter algorithms and architectures for ultra-high-speed network security applications.

Arish Sateesan, Jo Vliegen, Joan Daemen, Nele Mentens

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020