Arindam Mukherjee

Affiliations:
  • University of North Carolina at Charlotte, Charlotte, NC, USA
  • University of California, Santa Barbara, CA, USA (Ph.D., 2002)


According to our database1, Arindam Mukherjee authored at least 30 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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On csauthors.net:

Bibliography

2019
Fog Computing for Real-Time Accident Identification and Related Congestion Control.
Proceedings of the 2019 IEEE International Systems Conference, 2019

2013
A Cross-Stack Predictive Control Framework for Multimedia Applications.
Proceedings of the 2013 IEEE International Symposium on Multimedia, 2013

2012
A Survey of Communications and Networking Technologies for Energy Management in Buildings and Home Automation.
J. Comput. Networks Commun., 2012

Performance Modeling of Shared Memory Multiple Issue Multicore Machines.
Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

2011
A machine learning approach to modeling power and performance of chip multiprocessors.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2009
Efficient parallel testing and diagnosis of digital microfluidic biochips.
ACM J. Emerg. Technol. Comput. Syst., 2009

Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer.
Proceedings of the FCCM 2009, 2009

2008
A stream chip-multiprocessor for bioinformatics.
SIGARCH Comput. Archit. News, 2008

Fault-tolerant wearable computing system architecture for self-health management.
Proceedings of the 2008 IEEE International Conference on Electro/Information Technology, 2008

2007
Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters.
J. Low Power Electron., 2007

Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips.
J. Electron. Test., 2007

2006
Power Optimized Design of CMOS Programmable Gain Amplifiers.
J. Low Power Electron., 2006

Multiple fault diagnosis in digital microfluidic biochips.
ACM J. Emerg. Technol. Comput. Syst., 2006

Automated design flow for diode-based nanofabrics.
ACM J. Emerg. Technol. Comput. Syst., 2006

2005
Defect-oriented testing and diagnosis of digital microfluidics-based biochips.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Retiming and clock scheduling to minimize simultaneous switching.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Reducing crosstalk noise in high speed FPGAs.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

On the Reduction of Simultaneous Switching in SoCs.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003
PITIA: an FPGA for throughput-intensive applications.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Wave steering to integrate logic and physical syntheses.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Clock and Power Gating with Timing Closure.
IEEE Des. Test Comput., 2003

A practical CAD technique for reducing power/ground noise in DSM circuits.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components.
Proceedings of the 2002 Design, 2002

2001
Interconnect complexity-aware FPGA placement using Rent's rule.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Interconnect pipelining in a throughput-intensive FPGA architecture.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

A Global Routing Technique for Wave-Steering Design Methodology.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Latency and Latch Count Minimization in Wave Steered Circuits.
Proceedings of the 38th Design Automation Conference, 2001

2000
A novel high throughput reconfigurable FPGA architecture.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

1999
Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique.
Proceedings of the 36th Conference on Design Automation, 1999

Wave pipelining YADDs-a feasibility study.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999


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