Arindam Mallik
According to our database1,
Arindam Mallik
authored at least 43 papers
between 2004 and 2024.
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Bibliography
2024
SAfEPaTh: A System-Level Approach for Efficient Power and Thermal Estimation of Convolutional Neural Network Accelerator.
CoRR, 2024
Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Performance Modeling and Workload Analysis of Distributed Large Language Model Training and Inference.
Proceedings of the IEEE International Symposium on Workload Characterization, 2024
2023
IEEE J. Solid State Circuits, 2023
AIMC Modeling and Parameter Tuning for Layer-Wise Optimal Operating Point in DNN Inference.
IEEE Access, 2023
Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration.
ACM Trans. Design Autom. Electr. Syst., 2022
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the International Joint Conference on Neural Networks, 2021
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm<sup>2</sup> in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2019
CoRR, 2019
2018
Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2011
Automatic Extraction of Pipeline Parallelism for Embedded Software Using Linear Programming.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011
2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.
Proceedings of the 47th Design Automation Conference, 2010
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
MNEMEE: a framework for memory management and optimization of static and dynamic data in MPSoCs.
Proceedings of the 2010 International Conference on Compilers, 2010
2009
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009
2008
Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008
2007
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007
Proceedings of the Workshop on Experimental Computer Science, 2007
Automated task distribution in multicore network processors using statistical analysis.
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007
2006
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
IEICE Trans. Inf. Syst., 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005
2004
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004