Arijit Dutta

Orcid: 0000-0001-7204-1010

According to our database1, Arijit Dutta authored at least 13 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Comprehensive Review of Recent Developments in VANET for Traffic, Safety & Remote Monitoring Applications.
J. Netw. Syst. Manag., October, 2024

2023
A Hybrid Deep Learning Model-Based Intrusion Detection System for Emergency Planning Using IoT-Network.
Proceedings of the International Conference on Information and Communication Technologies for Disaster Management, 2023

2022
Automatic generation of the ground truth for tumor budding using H&E stained slides.
Proceedings of the Medical Imaging 2022: Digital and Computational Pathology, 2022

2021
MProve+: Privacy Enhancing Proof of Reserves Protocol for Monero.
IEEE Trans. Inf. Forensics Secur., 2021

Assisting fog-cloud computing with an adaptive traffic awareness resource provisioning algorithm for health data.
Proceedings of the 19th OITS International Conference on Information Technology, 2021

Finite Buffer Queueing System Performance Study with Multi Heterogeneous Fog Architecture.
Proceedings of the 19th OITS International Conference on Information Technology, 2021

2019
Revelio: A MimbleWimble Proof of Reserves Protocol.
IACR Cryptol. ePrint Arch., 2019

Nummatus: A Privacy Preserving Proof of Reserves Protocol for Quisquis.
Proceedings of the Progress in Cryptology - INDOCRYPT 2019, 2019

MProve: A Proof of Reserves Protocol for Monero Exchanges.
Proceedings of the 2019 IEEE European Symposium on Security and Privacy Workshops, 2019

2018
MProve: A Proof of Assets Protocol for Monero Exchanges.
IACR Cryptol. ePrint Arch., 2018

2008
Penalty for power reduction -: performance or schedule or yield?
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2001
Sub-100 nm CMOS circuit performance with high-K gate dielectrics.
Microelectron. Reliab., 2001

Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001


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