Arighna Deb

According to our database, Arighna Deb authored at least 29 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars.

Kousik Bhunia, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler

ACM Trans. Embed. Comput. Syst., November, 2024

In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures.

Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Leveraging ReRAM Sequence Graphs for Efficient Mapping of Binary Adders in ReRAM Crossbars.

Pragnya Dhal, Arighna Deb, Subrata Das, Debesh Kumar Das

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation.

Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Dynamic Realization of Multiple Control Toffoli Gate.

Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Impact of sneak paths on in-memory logic design in memristive crossbars.

Kamalika Datta, Arighna Deb, Abhoy Kole, Rolf Drechsler

it Inf. Technol., May, 2023

Verification of In-Memory Logic Design using ReRAM Crossbars.

Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring.

Subrata Das, Arighna Deb, Petr Fiser

Proceedings of the International Symposium on Devices, Circuits and Systems, 2023

Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network.

Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars.

Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2021

Exploring the Potential Benefits of Alternative Quantum Computing Architectures.

Arighna Deb, Gerhard W. Dueck, Robert Wille

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An Efficient Design for Testability Approach of Reversible Logic Circuits.

Joyati Mondal, Arighna Deb, Debesh K. Das

J. Circuits Syst. Comput., 2021

Design Space Exploration of Matrix-Matrix Convolution Operation.

Piyalee Behera, Arighna Deb

J. Circuits Syst. Comput., 2021

2020

Towards Exploring the Potential of Alternative Quantum Computing Architectures.

Arighna Deb, Gerhard W. Dueck, Robert Wille

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Delay Efficient All Optical Carry Lookahead Adder.

Sayantani Roy, Arighna Deb, Debesh K. Das

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Detailed Fault Model for Physical Quantum Circuits.

Arighna Deb, Debesh K. Das

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2017

An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata.

Arighna Deb, Debesh K. Das

Microprocess. Microsystems, 2017

Synthesis of optical circuits using binary decision diagrams.

Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler

Integr., 2017

OR-Inverter Graphs for the Synthesis of Optical Circuits.

Arighna Deb, Robert Wille, Rolf Drechsler

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs.

Arighna Deb, Robert Wille, Rolf Drechsler

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits.

Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler

ACM J. Emerg. Technol. Comput. Syst., 2016

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability.

Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya

ACM J. Emerg. Technol. Comput. Syst., 2016

2015

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization.

Arighna Deb, Robert Wille, Rolf Drechsler, Debesh K. Das

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014

A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic.

Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay

J. Low Power Electron., 2014

A regular network of symmetric functions in quantum-dot cellular automata.

Arighna Deb, Debesh Kumar Das

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Synthesis of Symmetric Boolean Functions Using a Three-Stage Network.

Arighna Deb, Debesh K. Das, Bhargab B. Bhattacharya

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2013

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure.

Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler

Proceedings of the Reversible Computation - 5th International Conference, 2013

Modular Design for Symmetric Functions Using Quantum Quaternary Logic.

Arighna Deb, Debesh K. Das, Susmita Sur-Kolay

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Reversible synthesis of symmetric boolean functions based on unate decomposition.

Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013