Ari Kulmala

Orcid: 0009-0005-5755-7402

According to our database1, Ari Kulmala authored at least 24 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading.
CoRR, 2024

2023
Towards Dependable RISC-V Cores for Edge Computing Devices.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023

2022
Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2019
Feasibility of FPGA accelerated IPsec on cloud.
Microprocess. Microsystems, 2019

2018
Live Demonstration: 4K100p HEVC Intra Encoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

FPGA-Powered 4K120p HEVC Intra Encoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Low Latency Edge Rendering Scheme for Interactive 360 Degree Virtual Reality Gaming.
Proceedings of the 38th IEEE International Conference on Distributed Computing Systems, 2018

2017
Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

2009
Scalable multiprocessor system-on-chip architecture design on FPGA.
PhD thesis, 2009

Evaluating SoC Network Performance in MPEG-4 Encoder.
J. Signal Process. Syst., 2009

2008
Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip.
IET Comput. Digit. Tech., 2008

On the credibility of load-latency measurement of network-on-chips.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

2007
Evaluating Large System-on-Chip on Multi-FPGA Platform.
Proceedings of the Embedded Computer Systems: Architectures, 2007

On network-on-chip comparison.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

IP Integration Overhead Analysis in System-on-Chip Video Encoder.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC.
EURASIP J. Embed. Syst., 2006

Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
HIBI-based multiprocessor SoC on FPGA.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005


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