Ari Kulmala

According to our database, Ari Kulmala authored at least 24 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation.

Luca Valente, Alessandro Nadalini, Asif Hussain Chiralil Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading.

Maicol Ciani, Emanuele Parisi, Alberto Musa, Francesco Barchi, Andrea Bartolini, Ari Kulmala, Rafail Psiakis, Angelo Garofalo, Andrea Acquaviva, Davide Rossi

CoRR, 2024

2023

Towards Dependable RISC-V Cores for Edge Computing Devices.

Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, Marcello Traiola

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs.

Luca Valente, Asif Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi

Proceedings of the 35th IEEE Hot Chips Symposium, 2023

2022

Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology.

Antti Rautakoura, Timo Hämäläinen, Ari Kulmala, Tero Lehtinen, Mehdi Duman, Mohamed Ibrahim

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2019

Feasibility of FPGA accelerated IPsec on cloud.

Markku Vajaranta, Arto Oinonen, Timo D. Hämäläinen, Vili Viitamäki, Jouni Markunmäki, Ari Kulmala

Microprocess. Microsystems, 2019

2018

Live Demonstration: 4K100p HEVC Intra Encoder.

Vili Viitamäki, Panu Sjövall, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

FPGA-Powered 4K120p HEVC Intra Encoder.

Panu Sjövall, Vili Viitamäki, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Low Latency Edge Rendering Scheme for Interactive 360 Degree Virtual Reality Gaming.

Marko Viitanen, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the 38th IEEE International Conference on Distributed Computing Systems, 2018

2017

Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server.

Panu Sjovall, Vili Viitamäki, Arto Oinonen, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

2009

Scalable multiprocessor system-on-chip architecture design on FPGA.

Ari Kulmala

PhD thesis, 2009

Evaluating SoC Network Performance in MPEG-4 Encoder.

Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen

J. Signal Process. Syst., 2009

2008

Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip.

Ari Kulmala, Erno Salminen, Timo D. Hämäläinen

IET Comput. Digit. Tech., 2008

On the credibility of load-latency measurement of network-on-chips.

Erno Salminen, Ari Kulmala, Timo Hämäläinen

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

2007

Evaluating Large System-on-Chip on Multi-FPGA Platform.

Ari Kulmala, Erno Salminen, Timo D. Hämäläinen

Proceedings of the Embedded Computer Systems: Architectures, 2007

On network-on-chip comparison.

Erno Salminen, Ari Kulmala, Timo D. Hämäläinen

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

IP Integration Overhead Analysis in System-on-Chip Video Encoder.

Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder.

Ari Kulmala, Erno Salminen, Timo D. Hämäläinen

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC.

Ari Kulmala, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen

EURASIP J. Embed. Syst., 2006

Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA.

Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA.

Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder.

Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005

HIBI-based multiprocessor SoC on FPGA.

Erno Salminen, Ari Kulmala, Timo D. Hämäläinen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC.

Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko Hännikäinen, Timo D. Hämäläinen

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005