Arghavan Asad
Orcid: 0000-0001-9254-9479
According to our database1,
Arghavan Asad
authored at least 32 papers
between 2009 and 2023.
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Bibliography
2023
2022
Future Internet, 2022
Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression.
CoRR, 2022
Proceedings of the Future Technologies Conference, 2022
Proceedings of the International Conference on Computational Science and Computational Intelligence, 2022
2021
A Power-Aware Hybrid Cache for Chip-Multi Processors Based on Neural Network Prediction Technique.
Int. J. Parallel Program., 2021
2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
2019
An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors.
J. Circuits Syst. Comput., 2019
An Energy-Efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors.
CoRR, 2019
Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
2018
A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age.
EURASIP J. Embed. Syst., 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses.
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018
2017
Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy.
Microprocess. Microsystems, 2017
Power Modeling and Runtime Performance Optimization of Power Limited Many-Core Systems Based on a Dynamic Adaptive Approach.
J. Low Power Electron., 2017
Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Reliability and Power Optimization in 3D-Stacked Cache Using a Run-Time Reconfiguration Procedure.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017
An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
A new traffic compression method for end-to-end memory accesses in 3D chip-multiprocessors.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
Exploiting non-uniformity of write accesses for designing a high-endurance hybrid Last Level Cache in 3D CMPs.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
2016
UCA: An Energy-efficient Hybrid Uncore Architecture in 3D Chip-Multiprocessors to minimize crosstalk.
Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016
High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
Lighting the Dark-Silicon 3D Chip Multi-processors by Exploiting Heterogeneity in Cache Hierarchy.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015
Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
2011
IEICE Electron. Express, 2011
2009
Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009