Ares Tahiraga

According to our database, Ares Tahiraga authored at least 3 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V.

Endri Kaja, Nicolas Gerlin, Ares Tahiraga, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs.

Endri Kaja, Nicolas Gerlin, Jad Al Halabi, Ares Tahiraga, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

2023

Bits, Flips and RISCs.

Nicolas Gerlin, Endri Kaja, Fabian Vargas, Li Lu, Anselm Breitenreiter, Junchao Chen, Markus Ulbricht, Maribel Gomez, Ares Tahiraga, Sebastian Prebeck, Eyck Jentzsch, Milos Krstic, Wolfgang Ecker

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023