Arefeh Soltani

According to our database1, Arefeh Soltani authored at least 8 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A low-jitter leakage-free digitally calibrated phase locked loop.
Comput. Electr. Eng., 2020

2016
Programmable incrementing/decrementing binary accumulator for high-speed calibration loops.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Fast and accurate fractional frequency synthesizer in 0.18μm technology.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

A 6-bit 800MS/s flash ADC in 0.35μm CMOS.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

A new ultra high speed 7-2 compressor with a new structure.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2014
A novel mixed-signal digital CMOS fuzzy logic controller in current mode.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014


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