Arda Yurdakul
Orcid: 0000-0001-7132-0042
According to our database1,
Arda Yurdakul
authored at least 46 papers
between 1999 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Common Subexpression-Based Compression and Multiplication of Sparse Constant Matrices.
IEEE Embed. Syst. Lett., June, 2024
2023
ElectAnon: A Blockchain-based, Anonymous, Robust, and Scalable Ranked-choice Voting Protocol.
Distributed Ledger Technol. Res. Pract., September, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
2022
A Decentralized Framework with Dynamic and Event-Driven Container Orchestration at the Edge.
Proceedings of the 2022 IEEE International Conferences on Internet of Things (iThings) and IEEE Green Computing & Communications (GreenCom) and IEEE Cyber, 2022
A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2021
Proceedings of the ACSW '21: 2021 Australasian Computer Science Week Multiconference, 2021
2020
Proceedings of the NOMS 2020, 2020
2019
Designing a Blockchain-Based IoT With Ethereum, Swarm, and LoRa: The Software Solution to Create High Availability With Minimal Security Risks.
IEEE Consumer Electron. Mag., 2019
2018
CoRR, 2018
WIP: Daily Life Oriented Indoor Localization by Fusion of Smartphone Sensors and Wi-Fi.
Proceedings of the 2018 IEEE International Conference on Smart Computing, 2018
Proceedings of the Crypto Valley Conference on Blockchain Technology, 2018
2017
Microprocess. Microsystems, 2017
Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures.
J. Syst. Archit., 2017
Integrating low-power IoT devices to a blockchain-based infrastructure: work-in-progress.
Proceedings of the Thirteenth ACM International Conference on Embedded Software 2017 Companion, 2017
2016
Taxim: A Toolchain for Automated and Configurable Simulation for Embedded Multiprocessor Design.
CoRR, 2016
An efficient mapping algorithm on 2-D mesh Network-on-Chip with reconfigurable switches.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the FPGAs for Software Programmers, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Microprocess. Microsystems, 2015
Proceedings of the 12th FPGAworld Conference 2015, 2015
Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015
2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
A dynamically reconfigurable architecture for emergency and disaster management in ITS.
Proceedings of the International Conference on Connected Vehicles and Expo, 2014
MIPT: Rapid exploration and evaluation for migrating sequential algorithms to multiprocessing systems with multi-port memories.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
A dynamically reconfigurable communication architecture for multicore embedded systems.
J. Syst. Archit., 2012
Proceedings of the 20th Signal Processing and Communications Applications Conference, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
2010
Introducing Hardware-in-Loop Concept to the Hardware/Software Co-design of Real-time Embedded Systems.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010
2009
Proceedings of the 24th International Symposium on Computer and Information Sciences, 2009
Design automation model for application-specific processors on reconfigurable fabric.
Proceedings of the Forum on specification and Design Languages, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
2007
Int. J. Imaging Syst. Technol., 2007
2006
Proceedings of the International Symposium on System-on-Chip, 2006
2005
2000
A synthesis tool for the multiplierless realization of FIR-based multirate DSP systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions.
J. VLSI Signal Process., 1999
Statistical methods for the estimation of quantization effects in FIR-based multirate systems.
IEEE Trans. Signal Process., 1999