Archisman Ghosh
Orcid: 0000-0002-0264-6687
According to our database1,
Archisman Ghosh
authored at least 28 papers
between 2020 and 2024.
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Bibliography
2024
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm.
J. Electron. Test., June, 2024
Switch Capacitor-Based Time-Varying Transfer Function for FCN and CNN MLSCA-Resistant AES256 in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2024
J. Circuits Syst. Comput., 2024
IACR Cryptol. ePrint Arch., 2024
R-STELLAR: A Resilient Synthesizable Signature Attenuation SCA Protection on AES-256 with built-in Attack-on-Countermeasure Detection.
IACR Cryptol. ePrint Arch., 2024
Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Towards Power and EM SCA Resilience.
IACR Cryptol. ePrint Arch., 2024
A 0.03mm<sup>2</sup> 100-250MHz Charge-Pump or Amplifier-Less Integrating Sub-Sampling PLL for Ultra-low Power Communication and Computing.
CoRR, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Proceedings of the 2024 Workshop on Attacks and Solutions in Hardware Security, 2024
2023
Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity.
ACM J. Emerg. Technol. Comput. Syst., October, 2023
PG-CAS: Pro-Active EM-SCA Probe Detection Using Switched-Capacitor-Based Patterned-Ground Co-Planar Capacitive Asymmetry Sensing.
IEEE Open J. Circuits Syst., 2023
Physical Time-Varying Transfer Function as Generic Low-Overhead Power-SCA Countermeasure.
IEEE Open J. Circuits Syst., 2023
A 334 μW 0.158 mm<sup>2</sup> ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom-Cook Multiplication.
IEEE J. Solid State Circuits, 2023
A 334µW 0.158mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber with Low-latency Striding Toom-Cook Multiplication Extended Version.
IACR Cryptol. ePrint Arch., 2023
A 334μW 0.158mm<sup>2</sup> ASIC for Post-Quantum Key-Encapsulation Mechanism Saber with Low-latency Striding Toom-Cook Multiplication Authors Version.
CoRR, 2023
Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation.
IEEE J. Solid State Circuits, 2022
A 334uW 0.158mm<sup>2</sup> Saber Learning with Rounding based Post-Quantum Crypto Accelerator.
CoRR, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
A Digital Cascoded Signature Attenuation Countermeasure with Intelligent Malicious Voltage Drop Attack Detector for EM/Power SCA Resilient Parallel AES-256.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
Improving Network Throughput by Hardware Realization of a Dynamic Content Caching Scheme for Information-Centric Networking (ICN).
Wirel. Pers. Commun., 2021
36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
Physical Time-Varying Transfer Functions as Generic Low-Overhead Power-SCA Countermeasure.
IACR Cryptol. ePrint Arch., 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020