Arash Fayyazi

According to our database, Arash Fayyazi authored at least 30 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

CHOSEN: Compilation to Hardware Optimization Stack for Efficient Vision Transformer Inference.

Mohammad Erfan Sadeghi, Arash Fayyazi, Suhas Somashekar, Massoud Pedram

CoRR, 2024

Scalable Superconductor Neuron with Ternary Synaptic Connections for Ultra-Fast SNN Hardware.

Mustafa Altay Karamuftuoglu, Beyza Zeynep Ucpinar, Arash Fayyazi, Sasan Razmkhah, Mehdi Kamal, Massoud Pedram

CoRR, 2024

PEANO-ViT: Power-Efficient Approximations of Non-Linearities in Vision Transformers.

Mohammad Erfan Sadeghi, Arash Fayyazi, Seyedarmin Azizi, Massoud Pedram

Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions.

Arash Fayyazi, Mahdi Nazemi, Arya Fayyazi, Massoud Pedram

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Automated Optimization of Deep Neural Networks: Dynamic Bit-Width and Layer-Width Selection via Cluster-Based Parzen Estimation.

Seyedarmin Azizi, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis.

Soheil Nazar Shahsavani, Arash Fayyazi, Mahdi Nazemi, Massoud Pedram

ACM Trans. Reconfigurable Technol. Syst., June, 2023

Sensitivity-Aware Mixed-Precision Quantization and Width Optimization of Deep Neural Networks Through Cluster-Based Tree-Structured Parzen Estimation.

Seyedarmin Azizi, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram

CoRR, 2023

BlendNet: Design and Optimization of a Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions.

Arash Fayyazi, Mahdi Nazemi, Armin Abdollahi, Massoud Pedram

CoRR, 2023

SNT: Sharpness-Minimizing Network Transformation for Fast Compression-friendly Pretraining.

Jung Hwan Heo, Seyedarmin Azizi, Arash Fayyazi, Mahdi Nazemi, Massoud Pedram

CoRR, 2023

A Fast Training-Free Compression Framework for Vision Transformers.

Jung Hwan Heo, Arash Fayyazi, Mahdi Nazemi, Massoud Pedram

CoRR, 2023

Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks.

Jingkai Hong, Arash Fayyazi, Amirhossein Esmaili, Mahdi Nazemi, Massoud Pedram

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Better Than Worst-Case Decoding for Quantum Error Correction.

Gokul Subramanian Ravi, Jonathan M. Baker, Arash Fayyazi, Sophia Fuhui Lin, Ali Javadi-Abhari, Massoud Pedram, Frederic T. Chong

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Have your QEC and Bandwidth too!: A lightweight cryogenic decoder for common / trivial errors, and efficient bandwidth + execution management otherwise.

Gokul Subramanian Ravi, Jonathan M. Baker, Arash Fayyazi, Sophia Fuhui Lin, Ali Javadi-Abhari, Massoud Pedram, Frederic T. Chong

CoRR, 2022

Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators.

Jung Hwan Heo, Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2021

qMC: A Formal Model Checking Verification Framework For Superconducting Logic.

Mustafa Munir, Aswin Gopikanna, Arash Fayyazi, Massoud Pedram, Shahin Nazarian

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic.

Mahdi Nazemi, Arash Fayyazi, Amirhossein Esmaili, Atharva Khare, Soheil Nazar Shahsavani, Massoud Pedram

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

ESPRESSO-GPU: Blazingly Fast Two-Level Logic Minimization.

Hitarth Kanakia, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Logic Verification of Ultra-Deep Pipelined Beyond-CMOS Technologies.

Arash Fayyazi, Shahin Nazarian, Massoud Pedram

CoRR, 2020

HIPE-MAGIC: a technology-aware synthesis and mapping flow for highly parallel execution of memristor-aided LoGIC.

Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning.

Mahdi Nazemi, Amirhossein Esmaili, Arash Fayyazi, Massoud Pedram

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

OCTAN: An On-Chip Training Algorithm for Memristive Neuromorphic Circuits.

Mohammad Ansari, Arash Fayyazi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity.

Arash Fayyazi, Souvik Kundu, Shahin Nazarian, Peter A. Beerel, Massoud Pedram

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology.

Alvin D. Wong, Kevin Su, Hang Sun, Arash Fayyazi, Massoud Pedram, Shahin Nazarian

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework.

Shahin Nazarian, Arash Fayyazi, Massoud Pedram

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning.

Karunveer Singh, Rishabh Gupta, Vikram Gupta, Arash Fayyazi, Massoud Pedram, Shahin Nazarian

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations.

Arash Fayyazi, Soheil Shababi, Pierluigi Nuzzo, Shahin Nazarian, Massoud Pedram

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits.

Mohammad Ansari, Arash Fayyazi, Ali BanaGozar, Mohammad Ali Maleki, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

An Ultra Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors.

Arash Fayyazi, Mohammad Ansari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram

IEEE Internet Things J., 2018

SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application.

Arash Fayyazi, Souvik Kundu, Shahin Nazarian, Peter A. Beerel, Massoud Pedram

CoRR, 2018

2016

SEERAD: A high speed yet energy-efficient rounding-based approximate divider.

Reza Zendegani, Mehdi Kamal, Arash Fayyazi, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016