Arash Ardakani
Orcid: 0000-0003-3274-2394
According to our database1,
Arash Ardakani
authored at least 28 papers
between 2013 and 2024.
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Bibliography
2024
SlimFit: Memory-Efficient Fine-Tuning of Transformer-based Models Using Training Dynamics.
Proceedings of the 2024 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies (Volume 1: Long Papers), 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2022
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2022, 2022
2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
2020
IEEE Trans. Computers, 2020
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020
A Regression-Based Method to Synthesize Complex Arithmetic Computations on Stochastic Streams.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019
Proceedings of the 7th International Conference on Learning Representations, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A low-complexity fully scalable interleaver/address generator based on a novel property of QPP interleavers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks.
Proceedings of the 5th International Conference on Learning Representations, 2017
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017
2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016
Hardware implementation of FIR/IIR digital filters using integral stochastic computation.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
2015
A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2013
An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013