Arani Sinha

Adit D. Singh

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Innovative Practices Track: Session 4 AI Applications in Test.

[BibT_eX]

[DOI]

Stefano Di Carlo

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Innovative Practices Track: Session 3 Test and Functional Safety Standards.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Functional State Extraction using Scan DFT.

[BibT_eX]

[DOI]

Ilya Wagner

Pankaj Pant

Proceedings of the IEEE International Test Conference, 2024

Generating Storage-Aware Test Sets Targeting Several Fault Models.

[BibT_eX]

[DOI]

Hari Addepalli

Irith Pomeranz

M. Enamul Amyeen

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023

Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2023

2022

Innovative Practices Track: Next Generation Test Standards.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Innovative Practices Track: Silent Data Errors.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Multi-die Parallel Test Fabric for Scalability and Pattern Reusability.

[BibT_eX]

[DOI]

Yonsang Cho

Jon Easter

Meizel V. Leiva Rojas

Proceedings of the IEEE International Test Conference, 2022

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults.

[BibT_eX]

[DOI]

Hari Addepalli

Irith Pomeranz

M. Enamul Amyeen

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.

[BibT_eX]

[DOI]

Sujay Pandey

Zhiwei Liao

Shreyas Nandi

Adit D. Singh

Abhijit Chatterjee

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Synergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction.

[BibT_eX]

[DOI]

Sandip Ray

Proceedings of the 26th IEEE European Test Symposium, 2021

2020

Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests.

[BibT_eX]

[DOI]

Ankit Shah

Raman Nayyar

IEEE Des. Test, 2020

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.

[BibT_eX]

[DOI]

Adit D. Singh

Abhijit Chatterjee

Proceedings of the IEEE International Test Conference, 2020

2019

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Analog/Mixed Signal IP DFx from a Foundry perspective.

[BibT_eX]

[DOI]

Salem Abdennadher

Yonghyun Kim

Proceedings of the IEEE Latin American Test Symposium, 2019

Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017

Innovative practices session 1C screening for layout sensitive defects.

[BibT_eX]

[DOI]

Nitin Chaudhary

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

DFM-aware fault model and ATPG for intra-cell and inter-cell defects.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2017

2013

Path selection based on static timing analysis considering input necessary assignments.

[BibT_eX]

[DOI]

Bo Yao

Irith Pomeranz

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2011

The bang for the buck with resiliency: Yield or field?

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

The buck stops with wafer test: Dream or reality?

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A Novel mechanism for speed characterization during delay test.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010

Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality?

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

2009

Panel: Analog Characterization and Test: The Long Road to Realization.

[BibT_eX]

[DOI]

Amitava Majumdar

Vasu Ganti

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults.

[BibT_eX]

[DOI]

Sandeep K. Gupta

Melvin A. Breuer

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

On-Chip Inductance in X Architecture Enabled Design.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006

Simulating the Effects of Process Variations on Capacitive Crosstalk.

[BibT_eX]

[DOI]

Shahin Nazarian

T. M. Mak

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2003

An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults.

[BibT_eX]

[DOI]

Sandeep K. Gupta

Melvin A. Breuer

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

1999

Validation and test generation for oscillatory noise in VLSI interconnects.

[BibT_eX]

[DOI]

Sandeep K. Gupta

Melvin A. Breuer

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction.

[BibT_eX]

[DOI]

Salim Chowdhury

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1994

Location of the Largest Empty Rectangle among Arbitrary Obstacles.

[BibT_eX]

[DOI]

Subhas C. Nandy