Apostolos P. Fournaris

Orcid: 0000-0002-4758-2349

According to our database1, Apostolos P. Fournaris authored at least 84 papers between 2003 and 2024.

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Bibliography

2024

2023
Energy Consumption Evaluation of Post-Quantum TLS 1.3 for Resource-Constrained Embedded Devices.
IACR Cryptol. ePrint Arch., 2023

Run-Time Detection of Malicious Behavior Based on Exploit Decomposition Using Deep Learning: A Feasibility Study on SysJoker.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Treating a different kind of patient: curing security weaknesses in digital health systems of the future.
Proceedings of the 9th International Workshop on Advances in Sensors and Interfaces, 2023

A Design Approach and Prototype Implementation for Factory Monitoring Based on Virtual and Augmented Reality at the Edge of Industry 4.0.
Proceedings of the 21st IEEE International Conference on Industrial Informatics, 2023

Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Running Longer To Slim Down: Post-Quantum Cryptography on Memory-Constrained Devices.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

CCSW '23: Cloud Computing Security Workshop.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023

Providing Security Assurance & Hardening for Open Source Software/Hardware: The SecOPERA approach.
Proceedings of the 28th IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks , 2023

2022
High-Level Synthesis design approach for Number-Theoretic Multiplier.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Performance Evaluation of Post-Quantum TLS 1.3 on Resource-Constrained Embedded Systems.
Proceedings of the Information Security Practice and Experience, 2022

Machine-Learning Assisted Side-Channel Attacks on RNS ECC Implementations Using Hybrid Feature Engineering.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2022

2021
Machine Learning Attacks and Countermeasures on Hardware Binary Edwards Curve Scalar Multipliers.
J. Sens. Actuator Networks, 2021

Performance Evaluation of Post-Quantum TLS 1.3 on Embedded Systems.
IACR Cryptol. ePrint Arch., 2021

Empowering cyberphysical systems of systems with intelligence.
CoRR, 2021

High-Level Synthesis design approach for Number-Theoretic Transform Implementations.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Design and Performance Evaluation of an Embedded EDHOC Module.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021

Studying OpenCL-based Number Theoretic Transform for heterogeneous platforms.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Side Channel Assessment Platforms and Tools for Ubiquitous Systems.
Proceedings of the Security of Ubiquitous Computing Systems, 2021

2020
Privacy Preservation in Industrial IoT via Fast Adaptive Correlation Matrix Completion.
IEEE Trans. Ind. Informatics, 2020

Anomaly Detection Trusted Hardware Sensors for Critical Infrastructure Legacy Devices.
Sensors, 2020

Machine-Learning assisted Side-Channel Attacks on RNS-based Elliptic Curve Implementations using Hybrid Feature Engineering.
IACR Cryptol. ePrint Arch., 2020

Improved Hybrid Approach for Side-Channel Analysis Using Efficient Convolutional Neural Network and Dimensionality Reduction.
IEEE Access, 2020

Profiling Dilithium Digital Signature Traces for Correlation Differential Side Channel Attacks.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Decentralized, Secure and Cognitive Architecture for Automotive CyberPhysical System of Systems.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

CPSoSaware: Cross-Layer Cognitive Optimization Tools & Methods for the Lifecycle Support of Dependable CPSoS.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019
Practical Evaluation of Protected Residue Number System Scalar Multiplication.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

An efficient multi-parameter approach for FPGA hardware Trojan detection.
Microprocess. Microsystems, 2019

Design and leakage assessment of side channel attack resistant binary edwards Elliptic Curve digital signature algorithm architectures.
Microprocess. Microsystems, 2019

Components and Tools for Large Scale, Complex Cyber-Physical Systems Based on Industrial Internet of Things Technologies.
ERCIM News, 2019

Introducing Hardware-Based Intelligence and Reconfigurability on Industrial IoT Edge Nodes.
IEEE Des. Test, 2019

Generative Adversarial Networks in AI-Enabled Safety-Critical Systems: Friend or Foe?
Computer, 2019

Enabling the human in the loop: Linked data and knowledge in industrial cyber-physical systems.
Annu. Rev. Control., 2019

Evaluating CoAP End to End Security for Constrained Wireless Sensor Networks.
Proceedings of the 10th IFIP International Conference on New Technologies, 2019

Robust and Efficient Privacy Preservation in Industrial IoT via correlation completion and tracking.
Proceedings of the 17th IEEE International Conference on Industrial Informatics, 2019

Revisiting Rowhammer Attacks in Embedded Systems.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

Design and Run-Time Aspects of Secure Cyber-Physical Systems.
Proceedings of the Security and Quality in Cyber-Physical Systems Engineering, 2019

2018
Trusted hardware sensors for anomaly detection in critical infrastructure systems.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

IoT Integration for Adaptive Manufacturing.
Proceedings of the 21st IEEE International Symposium on Real-Time Distributed Computing, 2018

A flexible leakage trace collection setup for arbitrary cryptographic IP cores.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

An FPGA Hardware Trojan Detection Approach Based on Multiple Parameter Analysis.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
Hardware Security for Critical Infrastructures - The CIPSEC Project Approach.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Secure and Efficient RNS Software Implementation for Elliptic Curve Cryptography.
Proceedings of the 2017 IEEE European Symposium on Security and Privacy Workshops, 2017

Production process adaptation to IoT triggered manufacturing resource failure events.
Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, 2017

A Design Strategy for Digit Serial Multiplier Based Binary Edwards Curve Scalar Multiplier Architectures.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Security and Efficiency Analysis of One Time Password Techniques.
Proceedings of the 20th Pan-Hellenic Conference on Informatics, 2016

A High Speed Scalar Multiplier for Binary Edwards Curves.
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016

Residue Number System as a side channel and fault injection attack countermeasure in elliptic curve cryptography.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015
Comparing design approaches for elliptic curve point multiplication over <i>GF</i>(2<sup>k</sup>) with polynomial basis representation.
Microprocess. Microsystems, 2015

Challenges in designing trustworthy cryptographic co-processors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Designing efficient elliptic Curve Diffie-Hellman accelerators for embedded systems.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fault and Power Analysis Attack Resistant RNS based Edwards Curve Point Multiplication.
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015

Affine Coordinate Binary Edwards Curve Scalar Multiplier with Side Channel Attack Resistance.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Secure embedded system hardware design - A flexible security and trust enhanced approach.
Comput. Electr. Eng., 2014

Designing and Evaluating High Speed Elliptic Curve Point Multipliers.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
A Distributed Approach of a Threshold Certificate-Based Encryption Scheme with No Trusted Entities.
Inf. Secur. J. A Glob. Perspect., 2013

2012
Distributed Threshold Certificate based Encryption Scheme with No Trusted Dealer.
Proceedings of the SECRYPT 2012, 2012

Protecting CRT RSA against Fault and Power Side Channel Attacks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

CRT RSA Hardware Architecture with Fault and Simple Power Attack Countermeasures.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Distributed Threshold Cryptography Certification with No Trusted Dealer.
Proceedings of the SECRYPT 2011 - Proceedings of the International Conference on Security and Cryptography, Seville, Spain, 18, 2011

Efficient CRT RSA with SCA Countermeasures.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Trust Ensuring Crisis Management Hardware Module.
Inf. Secur. J. A Glob. Perspect., 2010

Trust Management Through Hardware Means: Design Concerns and Optimizations.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Hardware Module Design for Ensuring Trust.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Fault and simple power attack resistant RSA using Montgomery modular multiplication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
An RNS Implementation of an F<sub>p</sub> Elliptic Curve Point Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Improved throughput bit-serial multiplier for GF(2<sup>m</sup>) fields.
Integr., 2009

Software and Hardware Issues in Smart Card Technology.
IEEE Commun. Surv. Tutorials, 2009

Low Area Elliptic Curve Arithmetic Unit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Σχεδιασμός κρυπτογραφικών συστημάτων δημοσίου κλειδιού
PhD thesis, 2008

Versatile multiplier architectures in GF(2<sup>k</sup>) fields using the Montgomery multiplication algorithm.
Integr., 2008

Creating an Elliptic Curve arithmetic unit for use in elliptic curve cryptography.
Proceedings of 13th IEEE International Conference on Emerging Technologies and Factory Automation, 2008

2007
A Low Power Design for Sbox Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users.
J. Low Power Electron., 2007

Applying systolic multiplication-inversion architectures based on modified extended Euclidean algorithm for GF(2<sup>k</sup>) in elliptic curve cryptography.
Comput. Electr. Eng., 2007

2006
An RNS architecture of an F<sub>p</sub> elliptic curve point multiplier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Applying Low Power Techniques in AES MixColumn/InvMixColumn Transformations.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Systolic Inversion Architecture Based on Modified Extended Euclidean Algorithm for GF(2K) Fields.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A new RSA encryption architecture and hardware implementation based on optimized Montgomery multiplication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel systolic GF(2k) field Multiplication-Inversion arithmetic unit.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

A systolic trinomial GF(2k) multiplier based on the Montgomery Multiplication Algorithm.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
GF(2<sup>K</sup>) multipliers based on Montgomery Multiplication Algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
VLSI architecture and FPGA implementation of ICE encryption algorithm.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003


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