Anuradha Agarwal

According to our database, Anuradha Agarwal authored at least 10 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

6-channel CMOS-based instrument for optical absorption spectroscopy and chemical identification.

Francesco Zanetto, Katherine Stoll, Samuel Serna, Anuradha Agarwal, Marco Sampietro, Giorgio Ferrari

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2019

Energy Efficiency of Microring Resonator (MRR)-Based Binary Decision Diagram (BDD) Circuits.

Ozan Yakar, Yuqi Nie, Kazumi Wada, Anuradha Agarwal, Ilke Ercan

Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019

2005

Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams.

Huiying Yang, Anuradha Agarwal, Ranga Vemuri

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners.

Anuradha Agarwal, Ranga Vemuri

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits.

Anuradha Agarwal, Ranga Vemuri

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits.

Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

A high level language for pre-layout extraction in parasite-aware analog circuit synthesis.

Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.

Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen

Proceedings of the 2004 Design, 2004

Accurate Estimation of Parasitic Capacitances in Analog Circuits.

Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri

Proceedings of the 2004 Design, 2004

Fast and accurate parasitic capacitance models for layout-aware.

Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri

Proceedings of the 41th Design Automation Conference, 2004