Anupam Chattopadhyay
Orcid: 0000-0002-8818-6983Affiliations:
- Nanyang Technological University, Singapore
- RWTH Aachen University, Germany
According to our database1,
Anupam Chattopadhyay
authored at least 315 papers
between 2004 and 2024.
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Bibliography
2024
Image Compression Based on Near Lossless Predictive Measurement Coding for Block-Based Compressive Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
IEEE Trans. Veh. Technol., April, 2024
Side-channel and Fault-injection attacks over Lattice-based Post-quantum Schemes (Kyber, Dilithium): Survey and New Results.
ACM Trans. Embed. Comput. Syst., March, 2024
ACM Trans. Embed. Comput. Syst., March, 2024
Machine Learning based Blind Side-Channel Attacks on PQC-based KEMs - A Case Study of Kyber KEM.
IACR Cryptol. ePrint Arch., 2024
Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation (Extended Version).
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
Federated Learning Optimization: A Comparative Study of Data and Model Exchange Strategies in Dynamic Networks.
CoRR, 2024
Efficient Quantum Circuits for Machine Learning Activation Functions including Constant T-depth ReLU.
CoRR, 2024
Authenticating Edge Neural Network through Hardware Security Modules and Quantum-Safe Key Management.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Boosting the Efficiency of Quantum Divider through Effective Design Space Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
PUF-based Lightweight Mutual Authentication Protocol for Internet of Things (IoT) Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024
2023
IET Quantum Commun., December, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
ACM Trans. Embed. Comput. Syst., 2023
Fiddling the Twiddle Constants - Fault Injection Analysis of the Number Theoretic Transform.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
Pushing the Limits of Generic Side-Channel Attacks on LWE-based KEMs - Parallel PC Oracle Attacks on Kyber KEM and Beyond.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
AI Attacks AI: Recovering Neural Network architecture from NVDLA using AI-assisted Side Channel Attack.
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 2023 Secure and Trustworthy Deep Learning Systems Workshop, 2023
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Invited Paper: Machine Learning Based Blind Side-Channel Attacks on PQC-Based KEMs - A Case Study of Kyber KEM.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
CRYSTALS-Dilithium on RISC-V Processor: Lightweight Secure Boot Using Post-Quantum Digital Signature.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
On Exploiting Message Leakage in (Few) NIST PQC Candidates for Practical Message Recovery Attacks.
IEEE Trans. Inf. Forensics Secur., 2022
Will You Cross the Threshold for Me? Generic Side-Channel Assisted Chosen-Ciphertext Attacks on NTRU-based KEMs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
Side-channel and Fault-injection attacks over Lattice-based Post-quantum Schemes (Kyber, Dilithium): Survey and New Results.
IACR Cryptol. ePrint Arch., 2022
IACR Cryptol. ePrint Arch., 2022
IACR Cryptol. ePrint Arch., 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the IEEE International Conference on Trust, 2022
How Many Cameras Do You Need? Adversarial Attacks and Countermeasures for Robust Perception in Autonomous Vehicles.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2022
Proceedings of the Progress in Cryptology - INDOCRYPT 2022, 2022
Proceedings of the 42nd IEEE International Conference on Distributed Computing Systems, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE).
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
IEEE Trans. Parallel Distributed Syst., 2021
IEEE Internet Things J., 2021
IACR Cryptol. ePrint Arch., 2021
Three Input Exclusive-OR Gate Support For Boyar-Peralta's Algorithm (Extended Version).
IACR Cryptol. ePrint Arch., 2021
CAAI Trans. Intell. Technol., 2021
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
On Threat of Hardware Trojan to Post-Quantum Lattice-Based Schemes: A Key Recovery Attack on SABER and Beyond.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2021
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2021
Proceedings of the Progress in Cryptology - INDOCRYPT 2021, 2021
Proceedings of the 20th IEEE International Conference on Machine Learning and Applications, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Topics in Cryptology - CT-RSA 2021, 2021
2020
IEEE Trans. Inf. Forensics Secur., 2020
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020
IEEE Trans. Computers, 2020
J. Multiple Valued Log. Soft Comput., 2020
On Configurable SCA Countermeasures Against Single Trace Attacks for the NTT - A Performance Evaluation Study over Kyber and Dilithium on the ARM Cortex-M4.
IACR Cryptol. ePrint Arch., 2020
On Exploiting Message Leakage in (few) NIST PQC Candidates for Practical Message Recovery and Key Recovery Attacks.
IACR Cryptol. ePrint Arch., 2020
Drop by Drop you break the rock - Exploiting generic vulnerabilities in Lattice-based PKE/KEMs using EM-based Physical Attacks.
IACR Cryptol. ePrint Arch., 2020
Preliminary Hardware Benchmarking of a Group of Round 2 NIST Lightweight AEAD Candidates.
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version).
IACR Cryptol. ePrint Arch., 2020
IEEE Consumer Electron. Mag., 2020
Identification and utilization of copy number information for correcting Hi-C contact map of cancer cell lines.
BMC Bioinform., 2020
Hierarchical discovery of large-scale and focal copy number alterations in low-coverage cancer genomes.
BMC Bioinform., 2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2020
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Cyber Security Protocol for Secure Traffic Monitoring Systems using PUF-based Key Management.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020
Authentication Protocol for Secure Automotive Systems: Benchmarking Post-Quantum Cryptography.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 40th IEEE International Conference on Distributed Computing Systems, 2020
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures.
IET Comput. Digit. Tech., 2019
IACR Cryptol. ePrint Arch., 2019
Exploiting Determinism in Lattice-based Signatures - Practical Fault Attacks on pqm4 Implementations of NIST candidates.
IACR Cryptol. ePrint Arch., 2019
On Misuse of Nonce-Misuse Resistance: Adapting Differential Fault Attacks on (few) CAESAR Winners.
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
Mind the Portability: A Warriors Guide through Realistic Profiled Side-channel Analysis.
IACR Cryptol. ePrint Arch., 2019
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm.
CoRR, 2019
CoRR, 2019
Cryptogr. Commun., 2019
Proceedings of the 17th International Conference on Virtual-Reality Continuum and its Applications in Industry, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Analysis of the Strict Avalanche Criterion in Variants of Arbiter-Based Physically Unclonable Functions.
Proceedings of the Progress in Cryptology - INDOCRYPT 2019, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 2019 International Conference on Cyberworlds, 2019
Number "Not Used" Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2019
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2018
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization.
IEEE Trans. Parallel Distributed Syst., 2018
Toward Threat of Implementation Attacks on Substation Security: Case Study on Fault Detection and Isolation.
IEEE Trans. Ind. Informatics, 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Domain Wall Motion-Based Dual-Threshold Activation Unit for Low-Power Classification of Non-Linearly Separable Functions.
IEEE Trans. Biomed. Circuits Syst., 2018
Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things.
Proc. IEEE, 2018
A template-based technique for efficient Clifford+T-based quantum circuit implementation.
Microelectron. J., 2018
ACM J. Emerg. Technol. Comput. Syst., 2018
J. Cryptogr. Eng., 2018
Side-channel Assisted Existential Forgery Attack on Dilithium - A NIST PQC candidate.
IACR Cryptol. ePrint Arch., 2018
Number "Not" Used Once - Key Recovery Fault Attacks on LWE Based Lattice Cryptographic Schemes.
IACR Cryptol. ePrint Arch., 2018
IACR Cryptol. ePrint Arch., 2018
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization.
CoRR, 2018
Floating Point Multiplication Mapping on ReRAM Based In-memory Computing Architecture.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Crack me if you can: hardware acceleration bridging the gap between practical and theoretical cryptanalysis?: a Survey.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the 9th IFIP International Conference on New Technologies, 2018
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018
Proceedings of the IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2018
An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Secure and Tamper-resilient Distributed Ledger for Data Aggregation in Autonomous Vehicles.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
Parallel Process. Lett., 2017
Microelectron. J., 2017
Attacks in Reality: the Limits of Concurrent Error Detection Codes Against Laser Fault Injection.
J. Hardw. Syst. Secur., 2017
Efficient implementation of generalized Maiorana-McFarland class of cryptographic functions.
J. Cryptogr. Eng., 2017
IACR Cryptol. ePrint Arch., 2017
IACR Cryptol. ePrint Arch., 2017
A Comprehensive Performance Analysis of Hardware Implementations of CAESAR Candidates.
IACR Cryptol. ePrint Arch., 2017
Looting the LUTs : FPGA Optimization of AES and AES-like Ciphers for Authenticated Encryption.
IACR Cryptol. ePrint Arch., 2017
An analysis of root functions - A subclass of the Impossible Class of Faulty Functions (ICFF).
Discret. Appl. Math., 2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Automatic Test Pattern Generation for Multiple Missing Gate Faults in Reversible Circuits - Work in Progress Report.
Proceedings of the Reversible Computation - 9th International Conference, 2017
Proceedings of the Reversible Computation - 9th International Conference, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
ACM Trans. Embed. Comput. Syst., 2016
Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes.
IEEE Trans. Computers, 2016
J. Cryptogr. Eng., 2016
CoRR, 2016
CoRR, 2016
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 13th International Joint Conference on e-Business and Telecommunications (ICETE 2016), 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices.
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
A low overhead error confinement method based on application statistical characteristics.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Statistical fault injection for impact-evaluation of timing errors on application performance.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Bypassing Parity Protected Cryptography using Laser Fault Injection in Cyber-Physical System.
Proceedings of the 2nd ACM International Workshop on Cyber-Physical System Security, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IACR Cryptol. ePrint Arch., 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
J. Cryptogr. Eng., 2014
Ancilla-Quantum Cost Trade-off during Reversible Logic Synthesis using Exclusive Sum-of-Products.
CoRR, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Tutorial T2B: Cost / Application / Time to Market Driven SoC Design and Manufacturing Strategy.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Constructive Reversible Logic Synthesis for Boolean Functions with Special Properties.
Proceedings of the Reversible Computation - 6th International Conference, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the Progress in Cryptology - INDOCRYPT 2014, 2014
Proceedings of the Progress in Cryptology - INDOCRYPT 2014, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Information Security and Cryptology - 10th International Conference, 2014
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
2013
VLSI Design, 2013
IEEE Trans. Computers, 2013
IACR Cryptol. ePrint Arch., 2013
Three Snakes in One Hole: A 67 Gbps Flexible Hardware for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes.
IACR Cryptol. ePrint Arch., 2013
Optimized GPU Implementation and Performance Analysis of HC Series of Stream Ciphers.
IACR Cryptol. ePrint Arch., 2013
Cryptogr. Commun., 2013
Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
RAPID-FeinSPN: A Rapid Prototyping Framework for Feistel and SPN-Based Block Ciphers.
Proceedings of the Information Systems Security - 9th International Conference, 2013
Proceedings of the 4th Annual International Conference on Energy Aware Computing Systems and Applications, 2013
SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection.
Proceedings of the IEEE 14th International Conference on High Performance Switching and Routing, 2013
Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the Progress in Cryptology, 2013
2012
High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures.
Int. J. Reconfigurable Comput., 2012
Exploring security-performance trade-offs during hardware accelerator design of stream cipher RC4.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the Progress in Cryptology - INDOCRYPT 2011, 2011
2010
Int. J. Embed. Real Time Commun. Syst., 2010
2009
Microelectron. J., 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embed. Comput. Syst., 2008
J. Comput., 2008
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Proceedings of the 2004 Design, 2004