Anup P. Jose

According to our database, Anup P. Jose authored at least 13 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop.

Mohamed Badr Younis, Mostafa Gamal Ahmed, Tianyu Wang, Ahmed E. AbdelRahman, Mahmoud A. Khalil, Anup P. Jose, Pavan Kumar Hanumolu

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process.

Tianyu Wang, Da Wei, Ranick Ng, Gaurav Malhotra, Anup P. Jose, Amir Amirkhany, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2022

2019

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process.

Anup P. Jose, Valentin Abramzon, Mohamed Elzeftawi, Michael Wang, Kyunglok Kim, Younghoon Song, Shiva Moballegh, Jalil Kamali, Amir Amirkhany

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2015

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS.

Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang

IEEE J. Solid State Circuits, 2015

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.

Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.

Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs.

Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang

IEEE J. Solid State Circuits, 2013

2007

Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication.

Anup P. Jose, Kenneth L. Shepard

IEEE J. Solid State Circuits, 2007

2006

Pulsed current-mode signaling for nearly speed-of-light intrachip communication.

Anup P. Jose, George Patounakis, Kenneth L. Shepard

IEEE J. Solid State Circuits, 2006

Distributed Loss Compensation for Low-latency On-chip Interconnects.

Anup P. Jose, Kenneth L. Shepard

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

On-Chip Spectrum Analyzer for Analog Built-In Self Test.

Anup P. Jose, Keith A. Jenkins, Scott K. Reynolds

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

An on-chip jitter measurement circuit with sub-picosecond resolution.

Keith A. Jenkins, Anup P. Jose, David F. Heidel

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2003

Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application.

Yee William Li, George Patounakis, Anup P. Jose, Kenneth L. Shepard, Steven M. Nowick

Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003