Anup Gangwar

According to our database, Anup Gangwar authored at least 9 papers between 2002 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2021

An Automated Traffic Generation Framework for Performance Evaluation of Networks-on-Chip for Real World Use Cases.

Sri Harsha Gade, Anup Gangwar, Ambica Prasad, Nitin Kumar Agarwal, Ravishankar Sreedharan

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip.

Anup Gangwar, Ravishankar Sreedharan, Ambica Prasad, Nitin Kumar Agarwal, Sri Harsha Gade

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Automated Synthesis of Custom Networks-on-Chip for Real World Applications.

Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad, Sri Harsha Gade, Zheng Xu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Traffic Driven Automated Synthesis of Network-on-Chip from Physically Aware Behavioral Specification.

Anup Gangwar, Zheng Xu, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2007

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.

Anup Gangwar, M. Balakrishnan, Anshul Kumar

ACM Trans. Design Autom. Electr. Syst., 2007

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.

Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar

Int. J. Parallel Program., 2007

2005

SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).

Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2003

SoC Synthesis with Automatic Hardware Software Interface Generation.

Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002

A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.

M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002